Datasheet

12-16 MCF5407 User’s Manual
DMA Controller Module Functional Description
Figure 12-12. Dual-Address, Peripheral-to-SDRAM, Lower-Priority DMA Transfer
Figure 12-13 shows a single-address DMA transfer in which the peripheral is reading from
memory. Note that TM2 is high, indicating a single-address transfer. Note that DREQ
is
negated in clock 4, before the assertion of TS
in clock 6.
AS
TIP
A[31:0]
SIZ[1:0]
D[31:0]
CS
x
TA
DRAMW
SRAS
SCAS
RAS[1:0]
CAS
[3:0]
TT[1:0]
TM2
DREQ0
TS
R/W
CLKIN
001 01
Precharge
CPU DMA Read CPU DMA Write CPU
TM0/DACK0