Datasheet

Tables xxxiii
TABLES
Table
Number
Title
Page
Number
15-3 Relationship between PADAT Register and Parallel Port Pin (PP) ........................... 15-3
16-1 Pins 1–52 (Left, Top-to-Bottom) ................................................................................ 16-1
16-2 Pins 53–104 (Bottom, Left-to-Right).......................................................................... 16-3
16-3 Pins 105–156 (Right, Bottom-to-Top)........................................................................ 16-5
16-4 Pins 157–208 (Top, Right-to-Left) ............................................................................. 16-6
16-5 Dimensions ............................................................................................................... 16-11
17-1 MCF5407 Signal Index............................................................................................... 17-3
17-2 MCF5407 Alphabetical Signal Index ......................................................................... 17-5
17-3 Data Pin Configuration ............................................................................................... 17-8
17-4 Bus Cycle Size Encoding............................................................................................ 17-9
17-5 Bus Cycle Transfer Type Encoding.......................................................................... 17-10
17-6 TM[2:0] Encodings for TT = 00 (Normal Access)................................................... 17-10
17-7 TM2 Encoding for DMA as Master (TT = 01)......................................................... 17-11
17-8 TM[1:0] Encoding for DMA as Master (TT = 01) ................................................... 17-11
17-9 TM[2:0] Encodings for TT = 10 (Emulator Access) ................................................ 17-11
17-10 TM[2:0] Encodings for TT = 11 (Interrupt Level) ................................................... 17-12
17-11 Data Pin Configuration ............................................................................................. 17-14
17-12 D7 Selection of CS0 Automatic Acknowledge ........................................................ 17-14
17-13 D6 and D5 Selection of CS0 Port Size ..................................................................... 17-14
17-14 D3/BE_CONFIG, BE[3:0] Boot Configuration ....................................................... 17-15
17-15 D4/ADDR_CONFIG, Address Pin Assignment....................................................... 17-15
18-1 ColdFire Bus Signal Summary ................................................................................... 18-1
18-2 Bus Cycle Size Encoding............................................................................................ 18-3
18-3 Accesses by Matches in CSCRs and DACRs ............................................................. 18-5
18-4 Bus Cycle States ......................................................................................................... 18-6
18-5 Allowable Line Access Patterns ............................................................................... 18-12
18-6 MCF5407 Arbitration Protocol States ...................................................................... 18-20
18-7 ColdFire Bus Arbitration Signal Summary............................................................... 18-21
18-8 Cycles for Basic No-Wait-State External Master Access......................................... 18-23
18-9 Cycles for External Master Burst Line Access to 32-Bit Port .................................. 18-24
18-10 MCF5407 Two-Wire Bus Arbitration Protocol Transition Conditions.................... 18-28
18-11 Three-Wire Bus Arbitration Protocol Transition Conditions ................................... 18-32
18-12 Data Pin Configuration ............................................................................................. 18-35
19-1 JTAG Pin Descriptions ............................................................................................... 19-3
19-2 JTAG Instructions....................................................................................................... 19-5
19-3 IDCODE Bit Assignments.......................................................................................... 19-6
19-4 Boundary-Scan Bit Definitions................................................................................... 19-7
20-1 Absolute Maximum Ratings ....................................................................................... 20-1
20-2 Operating Temperatures.............................................................................................. 20-1
20-3 DC Electrical Specifications ....................................................................................... 20-2
20-4 Divide Ratio Encodings .............................................................................................. 20-4
20-5 Clock Timing Specification ........................................................................................ 20-5
20-6 Input AC Timing Specification................................................................................... 20-6