Datasheet

Chapter 13. Timer Module 13-3
General-Purpose Timer Programming Model
• Reference compare—A timer can be configured to count up to a reference value, at
which point TERn[REF] is set. If TMRn[ORI] is one, an interrupt is issued. If the
free run/restart bit TMRn[FRR] is set, a new count starts. If it is clear, the timer
keeps running.
• Output mode—When a timer reaches the reference value selected by TMRn[OM],
it can send an output signal on TOUTn. TOUTn can be an active-low pulse or a
toggle of the current output under program control.
NOTE:
Although external devices cannot access MCF5407 on-chip
memories or MBAR, they can access timer module registers.
The timer module registers, shown in Table 13-1, can be modified at any time.
13.3.1 Timer Mode Registers (TMR0/TMR1)
Timer mode registers (TMR0/TMR1), Figure 13-2, program the prescaler and various
timer modes.
Table 13-2 describes TMRn fields.
Table 13-1. General-Purpose Timer Module Memory Map
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]
0x140 Timer 0 mode register (TMR0) [p. 13-3] Reserved
0x144 Timer 0 reference register (TRR0) [p. 13-4] Reserved
0x148 Timer 0 capture register (TCR0) [p. 13-4] Reserved
0x14C Timer 0 counter (TCN0) [p. 13-5] Reserved
0x150
Reserved Timer 0 event register
(TER0) [p. 13-5]
Reserved
0x180 Timer 1 mode register (TMR1) [p. 13-3] Reserved
0x184 Timer 1 reference register (TRR1) [p. 13-4] Reserved
0x188 Timer 1 capture register (TCR1) [p. 13-4] Reserved
0x18C Timer 1 counter (TCN1) [p. 13-5] Reserved
0x190
Reserved Timer 1 event register
(TER1) [p. 13-5]
Reserved
15 876543210
Field PS CE OM ORI FRR CLK RST
Reset 0000_0000_0000_0000
R/W R/W
Address MBAR + 0x140 (TMR0); + 0x180 (TMR1)
Figure 13-2. Timer Mode Registers (TMR0/TMR1)