Datasheet

Chapter 13. Timer Module 13-5
General-Purpose Timer Programming Model
clocking source and as an input capture pin.
13.3.4 Timer Counters (TCN0/TCN1)
The current value of the 16-bit, incrementing timer counters (TCN0/TCN1), Figure 13-5,
can be read anytime without affecting counting. Writing to TCNn clears it. The timer
counter decrements on the clock source rising edge (CLKIN ÷ 1, CLKIN ÷ 16, or TIN).
13.3.5 Timer Event Registers (TER0/TER1)
Each timer event register (TER0/TER1), Figure 13-6, reports capture or reference events
events the timer recognizes by setting TERn[CAP] or TERn[REF], which it does regardless
of the corresponding interrupt-enable bit values, TMRn[ORI,CE].
Writing a 1 to either REF or CAP clears it (writing a 0 does not affect bit value); both bits
can be cleared at the same time. REF and CAP must be cleared early in the exception
handler, before the timer negates the IRQ
n to the interrupt controller.
15 0
Field CAP (16-bit capture counter value)
Reset 0000_0000_0000_0000
R/W Read only
Address MBAR + 0x148 (TCR0); + 0x188 (TCR1)
Figure 13-4. Timer Capture Register (TCR0/TCR1)
15 0
Field 16-bit timer counter value count
Reset 0000_0000_0000_0000
R/W R/W (to reset)
Address MBAR + 0x14C (TCN0); + 0x18C (TCN1)
Figure 13-5. Timer Counters (TCN0/TCN1)
7210
Field — REF CAP
Reset 0000_0000
R/W R/W (ones clear/zeros have no effect)
Address MBAR + 0x151 (TER0); + 0x191 (TER1)
Figure 13-6. Timer Event Registers (TER0/TER1)