Datasheet

Chapter 14. UART Modules 14-3

• Each channel programmable to normal (full-duplex), automatic echo, local

loop-back, or remote loop-back mode

• Automatic wake-up mode for multidrop applications

• Four maskable interrupt conditions

• UART0 and UART1 have interrupt capability to DMA channels 2 and 3,

respectively, when either the RxRDY or FFULL bit is set in the USR.

• Parity, framing, and overrun error detection

• False-start bit detection

• Line-break detection and generation

• Detection of breaks originating in the middle of a character

• Start/end break interrupt/status

UART1 has the following additional features:

• Programmable to interface to an 8- or 16-bit CODEC for soft modem support

• Programmable to function as a digital AC ’97 controller

• Tx and Rx FIFOs can hold the following:

— 32 1-byte samples when programmed as a UART or as an 8-bit CODEC interface

— 16 2-byte samples when programmed as a 16-bit CODEC interface

— 16 20-bit samples when programmed as a digital AC ’97 controller

• Both DMA channels associated with the UARTs can be programmed to service

UART1 (one for the Tx channel and one for the Rx channel)

• No parity error, framing error, or line break detection in modem mode

14.3 Register Descriptions

This section contains a detailed description of each register and its speciﬁc function.

Flowcharts in Section 14.5.6, “Programming,” describe basic UART module programming.

The operation of the UART module is controlled by writing control bytes into the

appropriate registers. Table 14-1 is a memory map for UART module registers.