Datasheet

Chapter 14. UART Modules 14-5
Register Descriptions
NOTE:
UART registers are accessible only as bytes. Although external
masters cannot access on-chip memories or MBAR, they can
access any UART registers.
14.3.1 UART Mode Registers 1 (UMR1n)
The UART mode registers 1 (UMR1n) control configuration. UMR1n can be read or
written when the mode register pointer points to it, at RESET or after a
RESET MODE
REGISTER
POINTER command using UCRn[MISC]. After UMR1n is read or written, the
pointer points to UMR2n.
0x1DC 0x21C UART divider lower
registers—(UDLn) [p.
14-19]
—
0x1E0–
0x1EC
0x220–
0x22C
Do not access
2
—
0x1F0 0x230 UART interrupt vector
register—(UIVRn) [p.
14-20]
—
0x1F4 0x234 (Read) UART input
port registers—(UIPn)
[p. 14-20]
—
(Write) Do not access
2
—
0x1F8 0x238 (Read) Do not access
2
—
(Write) UART output
port bit set command
registers—(UOP1n
3
)
[p. 14-21]
—
0x1FC 0x23C (Read) Do not access
2
—
(Write) UART output
port bit reset
command
registers—(UOP0n
3
)
[p. 14-21]
—
1
UMR1n, UMR2n, and UCSRn should be changed only after the receiver/transmitter is issued a software reset
command. That is, if channel operation is not disabled, undesirable results may occur.
2
This address is for factory testing. Reading this location results in undesired effects and possible incorrect
transmission or reception of characters. Register contents may also be changed.
3
Address-triggered commands
Table 14-1. UART Module Programming Model (Continued)
MBAR Offset
[31:24] [23:16] [15:8] [7:0]
UART0 UART1