Datasheet

14-16 MCF5407 User’s Manual
Register Descriptions
Figure 14-13 shows the configuration of URB1.
14.3.12 UART Transmitter Buffers (UTBn)
The transmitter buffer for UART0 consists of the transmitter holding register and the
transmitter shift register. The holding register accepts characters from the bus master if
channel’s USRn[TxRDY] is set. A write to the transmitter buffer clears TxRDY, inhibiting
any more characters until the shift register can accept more data. When the shift register is
empty, it checks if the holding register has a valid character to be sent (TxRDY = 0). If there
is a valid character, the shift register loads it and sets USRn[TxRDY] again. Writes to the
transmitter buffer when the channel’s TxRDY = 0 and when the transmitter is disabled have
no effect on the transmitter buffer.
Figure 14-14 shows UTB0. TB contains the character in the transmitter buffer.
The transmitter buffer in UART1 consists of the transmitter shift register and the Tx FIFO,
as described in Section 14.5.2.6, “FIFOs in UART1.” The Tx FIFO in UART1 accepts
characters/samples from the bus master if there is room for them in the FIFO. A write to the
transmitter buffer clears TxRDY if the number of bytes in the FIFO exceeds the threshold
level in TXLVL. When the shift register is empty, it checks if the FIFO has a valid
character/sample to be sent. Valid characters are loaded into the shift register. Unlike UART
7 0
Field RB
Reset 0000_0000
R/W Read only
Address MBAR + 0x1CC
Figure 14-12. UART Receiver Buffer for UART0 (URB0)
31 24
23 16
15 8 7 0
Field
RB[31:24] RB[23:16] RB[15:8] RB[7:0]
Reset 0000_0000_0000_0000_0000_0000_0000_0000
R/W Read only
Address MBAR + 0x20C
Figure 14-13. UART Receiver Buffer for UART1 (URB1)
7 0
Field TB
Reset 0000_0000
R/W Write only
Address MBAR + 0x1CC
Figure 14-14. UART Transmitter Buffer for UART0 (UTB0)