Datasheet

Chapter 14. UART Modules 14-17
Register Descriptions
mode, in modem mode the Tx FIFO in UART1 can be loaded while the Tx is disabled. For
UART1, FIFOs can be accessed as longwords.
Figure 14-15 shows the configuration of the UTB1. These bits contain the samples in the
transmitter buffer for UART1.
14.3.13 UART Input Port Change Registers (UIPCRn)
The input port change registers (UIPCRn), Figure 14-16, hold the current state and the
change-of-state for CTS
.
Table 14-12 describes UIPCRn fields.
14.3.14 UART Auxiliary Control Register (UACRn)
The UART auxiliary control registers (UACRn), Figure 14-12, control the input enable.
31 24
23 16
15 8 7 0
Field
TB[31:24] TB[23:16] TB[15:8] TB[7:0]
Reset 0000_0000_0000_0000_0000_0000_0000_0000
R/W Write only
Address MBAR + 0x20C
Figure 14-15. UART Transmitter Buffer for UART1 (UTB1)
7 543 10
Field — COS 111 CTS
Reset 0000 0 11 CTS
R/W Read only
Address MBAR + 0x1D0 (UIPCR0), 0x210 (UIPCR1)
Figure 14-16. UART Input Port Change Register (UIPCRn)
Table 14-12. UIPCRn Field Descriptions
Bits Name Description
7–5 — Reserved, should be cleared.
4 COS Change of state (high-to-low or low-to-high transition). Not used in modem mode.
0 No change-of-state since the CPU last read UIPCRn. Reading UIPCRn clears UISRn[COS].
1 A change-of-state longer than 25–50 µs occurred on the CTS
input. UACRn can be programmed to
generate an interrupt to the CPU when a change of state is detected.
3–1 — Reserved, should be cleared.
0 CTS Current state. Starting two serial clock periods after reset, CTS reflects the state of CTS
. If CTS is
detected asserted at that time, COS is set, which initiates an interrupt if UACRn[IEC] is enabled. This
bit is not used in modem mode.
0 The current state of the CTS
input is asserted.
1 The current state of the CTS
input is negated.