Datasheet

xxxvi MCF5407 User’s Manual
Organization
— Chapter 3, “Hardware Multiply/Accumulate (MAC) Unit,” describes the
MCF5407 multiply/accumulate unit, which executes integer multiply,
multiply-accumulate, and miscellaneous register instructions. The MAC is
integrated into the operand execution pipeline (OEP).
— Chapter 4, “Local Memory.” This chapter describes the MCF5407
implementation of the ColdFire V4 local memory specification. It consists of the
two following major sections.
– Section 4.2, “SRAM Overview,” describes the MCF5407 on-chip static RAM
(SRAM) implementation. It covers general operations, configuration, and
initialization. It also provides information and examples showing how to
minimize power consumption when using the SRAM.
– Section 4.7, “Cache Overview,” describes the MCF5407 cache
implementation, including organization, configuration, and coherency. It
describes cache operations and how the cache interacts with other memory
structures.
— Chapter 5, “Debug Support,” describes the Revision C enhanced hardware debug
support in the MCF5407. This revision of the ColdFire debug architecture
encompasses earlier revisions.
• Part II, “System Integration Module (SIM),” describes the system integration
module, which provides overall control of the bus and serves as the interface
between the ColdFire core processor complex and internal peripheral devices. It
includes a general description of the SIM and individual chapters that describe
components of the SIM, such as the phase-lock loop (PLL) timing source, interrupt
controller for peripherals, configuration and operation of chip selects, and the
SDRAM controller.
— Chapter 6, “SIM Overview,” describes the SIM programming model, bus
arbitration, and system-protection functions for the MCF5407.
— Chapter 7, “Phase-Locked Loop (PLL),” describes configuration and operation
of the PLL module. It describes in detail the registers and signals that support the
PLL implementation.
— Chapter 8, “I2C Module,” describes the MCF5407 I
2
C module, including I
2
C
protocol, clock synchronization, and the registers in the I
2
C programing model.
It also provides extensive programming examples.
— Chapter 9, “Interrupt Controller,” describes operation of the interrupt controller
portion of the SIM. Includes descriptions of the registers in the interrupt
controller memory map and the interrupt priority scheme.
— Chapter 10, “Chip-Select Module,” describes the MCF5407 chip-select
implementation, including the operation and programming model, which
includes the chip-select address, mask, and control registers.
— Chapter 11, “Synchronous/Asynchronous DRAM Controller Module,”
describes configuration and operation of the synchronous/asynchronous DRAM