Datasheet

14-18 MCF5407 User’s Manual
Register Descriptions
Table 14-13 describes UACRn fields.
14.3.15 UART Interrupt Status/Mask Registers
(UISRn/UIMRn)
The UART interrupt status registers (UISRn), Figure 14-18, provide status for all potential
interrupt sources. UISRn contents are masked by UIMRn. If corresponding UISRn and
UIMRn bits are set, the internal interrupt output is asserted. If a UIMRn bit is cleared, the
state of the corresponding UISRn bit has no effect on the output.
NOTE:
True status is provided in the UISRn regardless of UIMRn
settings. UISRn is cleared when the UART module is reset.
Table 14-14 describes UISRn and UIMRn fields.
7 10
Field — IEC
Reset 0000_0000
R/W Write only
Address MBAR + 0x1D0 (UACR0), 0x210 (UACR1)
Figure 14-17. UART Auxiliary Control Register (UACRn)
Table 14-13. UACRn Field Descriptions
Bits Name Description
7–1 — Reserved, should be cleared.
0 IEC Input enable control. This bit is not used in modem mode.
0 Setting the corresponding UIPCRn bit has no effect on UISRn[COS].
1 UISRn[COS] is set and an interrupt is generated when the UIPCRn[COS] is set by an external
transition on the CTS
input (if UIMRn[COS] = 1).
76 32 1 0
Field COS — DB FFULL/RxRDY TxRDY
Reset 0000_0000
R/W Read only
Address MBAR + 0x1D4 (UISR0), 0x214 (UISR1); MBAR + 0x1D4 (UIMR0), 0x214 (UIMR1)
Figure 14-18. UART Interrupt Status/Mask Registers (UISRn/UIMRn)