Datasheet

Chapter 14. UART Modules 14-25
Operation
Let baud rate = 9600; the divider can be calculated as follows:
Therefore UDUn = 0x00 and UDLn = 0xB0.
14.5.1.2.2 External Clock
An external source clock (TIN) can be used as is or divided by 16.
14.5.2 Transmitter and Receiver Operating Modes
Figure 14-29 is a functional block diagram of the transmitter and receiver showing the
command and operating registers, which are described generally in the following sections
and described in detail in Section 14.3, “Register Descriptions.”
Figure 14-29. Transmitter and Receiver Functional Diagram
Baudrate
54MHz
32 divider×[]
------------------------------------=
Divider
54MHz
32 9600×[]
----------------------------- 176 decimal()0x00B0== =
Baudrate
Externalclockfrequency
16or1
---------------------------------------------------------------------=
Receiver Shift Register
UART Command Register (UCR0) W
UART Status Register (USR0)
R
Transmitter Shift Register
UART Mode Register 1 (UMR1) R/W
UART Mode Register 2 (UMR2) R/W
Transmitter Holding Register
W
Receiver Holding Register 3
Receiver Holding Register 2
Receiver Holding Register 1
R
UART Receive
UART
Buffer (URB0)
(4 Registers)
UART0
External
Interface
RXD
TXD
Transmitter Buffer
(UTB0)
(2 Registers)
FIFO (32-byte
FIFOs on
UART1)