Datasheet

Chapter 14. UART Modules 14-27
Operation
Figure 14-30. Transmitter Timing Diagram
14.5.2.2 Transmitter in Modem Mode (UART1)
After a hardware reset, UART1 is in UART mode. UART1 can be put in one of the modem
modes by writing the appropriate value for MODCTL[MODE], as described in
Section 14.3.4, “Modem Control Register (MODCTL).” The other MODCTL fields should
be initialized at the same time. Set the Tx FIFO threshold as described in Section 14.3.5,
“Tx FIFO Threshold Register (TXLVL).”
The serial bit clock is always an input to UART1 in modem mode (on CTS
). For an 8- or
16-bit CODEC, the frame sync is also an input to UART1 (on TIN1). However for an
AC ‘97 controller, UART1 provides the frame sync (on R
TS). Figure 14-31 shows an
example timing for UART1-CODEC interfaces (lsb first).
Figure 14-31. 16-Bit CODEC Interface Timing (lsb First)
C1
1
C2 C3 Break
C4 C6
TxD
Transmitter
Enabled
USRn[TxRDY]
W
2
WWWWWWW
CTS
3
RTS
4
Manually asserted
by BIT - SET command
Manually
asserted
Start
break
C5
not
transmitted
C6C4 Stop
break
C3C2C1
1
C1 in transmission
3
UMR2n[TxCTS] = 1
1
Cn = transmit characters
2
W = write
4
UMR2n [TxRTS] = 1
internal
module
select
CTS
TIN1
TxD
D0 D1 D2 D14 D15
D0 D1 D2 D14 D15
RxD
Frame Sync