Datasheet

14-28 MCF5407 User’s Manual
Operation
Figure 14-32 is an example timing diagram for the UART1-CODEC interface (msb first).
Figure 14-32. 8-Bit CODEC Interface Timing (msb First)
Figure 14-33 shows an example timing diagram for the UART1-AC ‘97 interface.
Figure 14-33. AC ‘97 Interface Timing
For more information about interfacing to an AC ‘97 controller, refer to the Audio
CODEC ‘97 Component Specification.
When interfaced to an 8- or 16-bit CODEC (MODCTL[MODE] = 01 or 10), UART1 starts
to send a sample either during the 1-bit clock cycle after the rising edge of frame sync,
according to the value of MODCTL[DTS1]. The width of the frame sync pulse makes no
difference. MODCTL[SHDIR] controls whether bits are shifted out msb or lsb first. After
the 8- or 16-bit sample is sent, zeros are sent until the next frame sync.
When interfacing to an AC ‘97 controller (MODCTL[MODE] = 11), UART1 starts to
transmit time slot 1 data one bit-clock cycle after the rising edge of frame sync, regardless
of the value of MODCTL[DTS1]. However, MODCTL[SHDIR] must be 0, because the
shift order must be msb first. UART1 divides the bit clock by 256 to generate a frame sync
pulse that is high for 16-bit clock cycles. The transmitter sends zeros until the receiver
detects the CODEC-ready condition (a 1 in the first bit of a new frame).
Because Rx data is sampled on the falling edge of the bit clock, for transmit purposes, the
frame has already started when the receiver detects a CODEC-ready condition. For this
reason, transmission starts at the next frame sync after the CODEC-ready condition is
detected. UART1 stops transmission at the end of the frame in which the first bit of the
received frame is detected low (CODEC not ready). During transmission, UART1 fills each
of the 13 time slots of the AC ‘97 frame with samples from the Tx FIFO.
CTS
TIN1
TxD
D7 D6 D5 D1 D0
D7 D6 D5 D1 D0RxD
Frame Sync
CTS
RTS
TxD
RxD
bit1 bit2 bit13 bit16
Slot 2 Slot 3 Slot 13 Slot 1
Slot 1
20 bits 20 bitsbit14 bit15
Frame
Slot 2 Slot 3 Slot 13 Slot 1
Frame Sync
Frame Sync
20 bits
bit1 bit2 bit13 bit16 20 bits 20 bitsbit14 bit15 20 bits