Datasheet

14-36 MCF5407 User’s Manual
Operation
Functional timing information for multidrop mode is shown in Figure 14-38.
Figure 14-38. Multidrop Mode Timing Diagram
A character sent from the master station consists of a start bit, a programmed number of
data bits, an address/data (A/D) bit flag, and a programmed number of stop bits. A/D = 1
indicates an address character; A/D = 0 indicates a data character. The polarity of A/D is
selected through UMR1n[PT]. UMR1n should be programmed before enabling the
transmitter and loading the corresponding data bits into the transmit buffer.
In multidrop mode, the receiver continuously monitors the received data stream, regardless
of whether it is enabled or disabled. If the receiver is disabled, it sets the RxRDY bit and
loads the character into the receiver holding register FIFO stack provided the received A/D
bit is a one (address tag). The character is discarded if the received A/D bit is zero (data
tag). If the receiver is enabled, all received characters are transferred to the CPU through
the receiver holding register stack during read operations.
In either case, the data bits are loaded into the data portion of the stack while the A/D bit is
loaded into the status portion of the stack normally used for a parity error (USRn[PE]).
Framing error, overrun error, and break detection operate normally. The A/D bit takes the
place of the parity bit; therefore, parity is neither calculated nor checked. Messages in this
mode may still contain error detection and correction information. One way to provide error
ADD1TxD
Transmitter
Enabled
USRn [TxRDY]
C0 ADD211
internal
module
select
A/D A/D A/D
ADD1RxD
Receiver
Enabled
USRn [RxRDY]
C0 ADD211
internal
module
select
A/D A/D A/D
0
A/D
0
A/D
(C0)
Status Data
(ADD 2)
Status DataADD 1
Peripheral Station
Master Station
UMR1n
[PM] = 11
UMR1n[PM] = 11
UMR1n[PT] = 1
ADD 1
UMR1n[PT] = 0
C0
UMR1n[PT] = 2
ADD 2
UMR1n[PM] = 11