Datasheet

Chapter 15. Parallel Port (General-Purpose I/O) 15-1
Chapter 15
Parallel Port (General-Purpose I/O)
This chapter describes the operation and programming model of the parallel port pin
assignment, direction-control, and data registers. It includes a code example for setting up
the parallel port.
15.1 Parallel Port Operation
The MCF5407 parallel port module has 16 signals, which are programmed as follows:
• The pin assignment register (PAR) selects the function of the 16 multiplexed pins.
• Port A data direction register (PADDR) determines whether pins configured as
parallel port signals are inputs or outputs.
• The Port A data register (PADAT) shows the status of the parallel port signals.
The operations of the PAR, PADDR, and PADAT are described in the following sections.
15.1.1 Pin Assignment Register (PAR)
The pin assignment register (PAR), which is part of the system integration module (SIM),
defines how each PAR bit determines each pin function, as shown in Figure 15-1.
If PP[9:8]/A[25:24] are unavailable because A[25:0] are needed for external addressing,
PP[15:10]/A[31:26] can be configured as general-purpose I/O. Table 15-1 summarizes
MCF5407 parallel port pins, described in detail in Chapter 17, “Signal Descriptions.”
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field PAR15 PAR14 PAR13 PAR12 PAR11 PAR10 PAR9 PAR8 PAR7 PAR6 PAR5 PAR4 PAR3 PAR2 PAR1 PAR0
PAR[n] = 0 PP15 PP14 PP13 PP12 PP11 PP10 PP9 PP8 PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0
PAR[n] = 1 A31 A30 A29 A28 A27 A26 A25 A24 TIP DREQ0 DREQ1 TM2 TM1/
DACK1
TM0/
DACK0
TT1 TT0
Reset Determined by driving D4/ADDR_CONFIG with a 1 or 0 when RSTI
negates. The system is configured as
PP[15:0] if D4 is low; otherwise alternate pin functions selected by PAR[n] = 1 are used.
R/W R/W
Address Address MBAR + 0x004
Figure 15-1. Parallel Port Pin Assignment Register (PAR)