Datasheet

IV-ii MCF5407 User’s Manual
Suggested Reading
The following literature may be helpful with respect to the topics in Part IV:
• IEEE Standard Test Access Port and Boundary-Scan Architecture
• IEEE Supplement to Standard Test Access Port and Boundary-Scan Architecture
(1149.1)
Acronyms and Abbreviations
Table IV-i describes acronyms and abbreviations used in Part IV.
Table IV-i. Acronyms and Abbreviated Terms
Term Meaning
BDM Background debug mode
BIST Built-in self test
BSDL Boundary-scan description language
DMA Direct memory access
DSP Digital signal processing
EDO Extended data output (DRAM)
GPIO General-purpose I/O
I
2
C Inter-integrated circuit
IEEE Institute for Electrical and Electronics Engineers
IPL Interrupt priority level
JEDEC Joint Electron Device Engineering Council
JTAG Joint Test Action Group
LSB Least-significant byte
lsb Least-significant bit
MAC Multiple accumulate unit
MBAR Memory base address register
MSB Most-significant byte
msb Most-significant bit
Mux Multiplex
PCLK Processor clock
PLL Phase-locked loop
POR Power-on reset
PQFP Plastic quad flat pack