Datasheet

Chapter 17. Signal Descriptions 17-5
Overview
Table 17-2 lists signals in alphabetical order by abbreviated name.
Timer outputs TOUT[1:0] Outputs waveform or pulse. O High 17-19
Section 17.11, “Parallel I/O Port (PP[15:0])”
17-19
Parallel port PP[15:0] Interfaces with I/O; multiplexed with
bus address and attribute signals.
I/O Input 17-19
Section 17.12, “I
2
C Module Signals”
17-20
Serial clock line SCL Clock signal for I
2
C operation I/O Open
drain
Up 17-20
Serial data line SDA Serial data port for I
2
C operation I/O Open
drain
Up 17-20
Section 17.13, “Debug and Test Signals”
17-20
Motorola test mode MTMOD0 Puts processor in functional or
emulator mode
I User cfg 17-20
Motorola test mode MTMOD[3:1] Reserved I Down 17-20
High impedance HIZ
Assertion three-states all outputs I Up 17-20
Processor clock out PSTCLK Output clock used for PSTDDATA O 17-21
Processor status/debug
data
PSTDDATA[7:0] Displays captured processor data
and breakpoint status
O Driven 17-21
Section 17.14, “Debug Module/JTAG Signals”
17-21
Test clock TCK Clock signal for IEEE 1149.1 JTAG I Low 17-22
Test reset/
Development serial
clock
TRST
/DSCLK Asynchronous reset for JTAG;
debug module clock input
I Up 17-21
Test mode select/
Breakpoint
TMS/BKPT
TMS (JTAG)/hardware breakpoint
(debug)
I Up 17-21
Test data input/
Development serial
input
TDI/DSI Multiplexed serial input for the JTAG
or background debug module
I Up 17-22
Test data output/
Development serial
output
TDO/DSO Multiplexed serial output for the
JTAG or background debug module
O Driven 17-22
1
If there is no arbiter, BG should be tied low; otherwise, it should be negated.
2
These data pins are sampled at reset for conguration.
Table 17-2. MCF5407 Alphabetical Signal Index
Abbreviation Signal Name Function I/O Page
AA_CONFIG Auto-acknowledge conguration Clock/reset I 17-14
ADDR_CONFIG Address conguration Clock/reset I 17-15
AS
Address strobe Bus I/O 17-9
Table 17-1. MCF5407 Signal Index (Continued)
Signal Name Abbreviation Function I/O Reset Pull-Up Page