Datasheet

17-10 MCF5407 User’s Manual
MCF5407 Bus Signals
external master access. This condition is indicated by the AM bit in the chip-select mask
register (CSMR) being cleared. See Chapter 10, “Chip-Select Module.”
17.2.8 Transfer In Progress (TIP/PP7)
The TIP/PP7 pin is programmed in the PAR to serve as the transfer-in-progress output or
as a parallel port bits. The TIP
output is asserted indicating a bus transfer is in progress. It
is negated during idle bus cycles if the bus is still granted to the processor. It is three-stated
for external master accesses. Note that TIP
is held asserted on back-to-back bus cycles.
17.2.9 Transfer Type (TT[1:0]/PP[1:0])
The TT[1:0]/PP[1:0] pins are programmed in the PAR to serve as the transfer type outputs
or as two parallel port bits. When the MCF5407 is bus master and TT[1:0] are enabled,
these signals are driven as outputs only. If an external master owns the bus and TT[1:0] are
enabled, these pins are three-stated by the MCF5407 and can be driven by the external
master. Table 17-5 shows the definition of the encodings.
17.2.10 Transfer Modifier (TM[2:0]/PP[4:2]/DACK[1:0])
The TM[2:0]/PP[4:2] pins are programmed in the PAR to serve as the transfer modifier
outputs or as three parallel port bits. These outputs provide supplemental information for
each transfer type; see Table 17-6 through Table 17-10.
When the MCF5407 is the bus master and TM[2:0] are enabled, these signals are driven as
outputs only. If an external device is bus master and TM[2:0] are enabled, these pins are
three-stated by the MCF5407 and can be driven by the external master.
Table 17-5. Bus Cycle Transfer Type Encoding
TT[1:0] Transfer Type
00 Normal access
01 DMA access
10 Emulator access
11 CPU space or interrupt acknowledge
Table 17-6. TM[2:0] Encodings for TT = 00 (Normal Access)
TM[2:0] Transfer Modifier
000 Cache push access
001 User data access
010 User code access
011–100 Reserved
101 Supervisor data access