Datasheet

17-20 MCF5407 User’s Manual
I2C Module Signals
Motorola recommends that D4 be driven during reset to a logic level.
17.12 I
2
C Module Signals
The I
2
C module acts as a two-wire, bidirectional serial interface between the MCF5407 and
peripherals with an I
2
C interface (such as LED controller, A-to-D converter, or D-to-A
converter). Devices connected to the I
2
C must have open-drain or open-collector outputs.
17.12.1 I
2
C Serial Clock (SCL)
The bidirectional, open-drain I
2
C serial clock signal (SCL) is the clock signal for I
2
C
module operation. The I
2
C module controls this signal when the bus is in master mode; all
I
2
C devices drive this signal to synchronize I
2
C timing.
17.12.2 I
2
C Serial Data (SDA)
The bidirectional, open-drain I
2
C serial data signal (SDA) is the data input/output for the
serial I
2
C interface.
17.13 Debug and Test Signals
The signals in this section interface with external I/O to provide processor status signals.
17.13.1 Test Mode (MTMOD[3:0])
The test mode signals choose between multiplexed debug module and JTAG signals. If
MTMOD0 is low, the part is in normal and background debug mode (BDM); if it is high,
it is in normal and JTAG mode. All other MTMOD values are reserved; MTMOD[3:1]
should be tied to ground and MTMOD[3:0] should not be changed while RSTI
is negated.
17.13.2 High Impedance (HIZ)
The assertion of HIZ forces all output drivers to high-impedance state. The timing on HIZ
is independent of the clock. Note that HIZ does not override the JTAG operation;
TDO/DSO can be forced to high impedance by asserting TRST
.
17.13.3 Processor Clock Output (PSTCLK)
The internal PLL generates this output signal, and is the processor clock output that is used
as the timing reference for the debug bus timing (PSTDDATA[7:0]). PSTCLK is at the
same frequency as the core processor and cache memory.