Datasheet

Chapter 17. Signal Descriptions 17-21
Debug Module/JTAG Signals
17.13.4 Processor Status Debug Data (PSTDDATA[7:0])
Processor status data outputs indicate both processor status and captured address and data
values. They operate at half the processor’s frequency, using PSTCLK. Given that real-time
trace information appears as a sequence of 4-bit data values, there are no alignment
restrictions; that is, PST values and operands may appear on either PSTDDATA[7:0]
nibble. The upper nibble, PSTDDATA[7:4], is most significant. See Chapter 5, “Debug
Support.”
17.14 Debug Module/JTAG Signals
The MCF5407 complies with the IEEE 1149.1a JTAG testing standard. JTAG test pins are
multiplexed with background debug pins. Except for TCK, these signals are selected by the
value of MTMOD0. If MTMOD0 is high, JTAG signals are chosen; if it is low, debug
module signals are chosen. MTMOD0 should be changed only while RSTI
is asserted.
17.14.1 Test Reset/Development Serial Clock
(TRST/DSCLK)
If MTMOD0 is high, TRST is selected. TRST asynchronously resets the internal JTAG
controller to the test logic reset state, causing the JTAG instruction register to choose the
bypass instruction. When this occurs, JTAG logic is benign and does not interfere with
normal MCF5407 functionality.
Although TRST
is asynchronous, Motorola recommends that it makes an
asserted-to-negated transition only while TMS is held high. TRST
has an internal pull-up
resistor so if it is not driven low, it defaults to a logic level of 1. If TRST
is not used, it can
be tied to ground or, if TCK is clocked, to V
DD
. Tying TRST to ground places the JTAG
controller in test logic reset state immediately. Tying it to V
DD
causes the JTAG controller
(if TMS is a logic level of 1) to eventually enter test logic reset state after 5 TCK clocks.
If MTMOD0 is low, DSCLK is selected. DSCLK is the development serial clock for the
serial interface to the debug module. The maximum DSCLK frequency is 1/5 CLKIN. See
Chapter 5, “Debug Support.”
17.14.2 Test Mode Select/Breakpoint (TMS/BKPT)
If MTMOD0 is high, TMS is selected. The TMS input provides information to determine
the JTAG test operation mode. The state of TMS and the internal 16-state JTAG controller
state machine at the rising edge of TCK determine whether the JTAG controller holds its
current state or advances to the next state. This directly controls whether JTAG data or
instruction operations occur. TMS has an internal pull-up resistor so that if it is not driven
low, it defaults to a logic level of 1. But if TMS is not used, it should be tied to V
DD
.
If MTMOD0 is low, BKPT
is selected. BKPT signals a hardware breakpoint to the