Datasheet

Chapter 18. Bus Operation 18-13
Data Transfer Operation
Figure 18-13. Line Read Burst (2-1-1-1), Internal Termination
Figure 18-14 shows a line access read with one wait state programmed in CSCRx to give
the peripheral or memory more time to return read data. This figure follows the same
execution as a zero-wait state read burst with the exception of an added wait state.
.
Figure 18-14. Line Read Burst (3-2-2-2), External Termination
Figure 18-15 shows a burst-inhibited line read access with fast termination. The external
device executes a basic read cycle while determining that a line is being transferred. The
external device uses fast termination for subsequent transfers.
TT[1:0]
R/W
TIP
TS
AS, CSx
D[31:0]
T
A
Read
Read
S0 S1 S2 S3 S4 S5 S10S9S8S7S6 S11 S12
Read
Read
CLKIN
BE
/BWEx, OE
TM[2:0], SIZ[1:0]
A[31:0]
A[31:0], TT[1:0]
R/W
TIP
TS
AS, CSx
D[31:0]
T
A
Read
S0
S1 S2
S3
S4
S5
S10
S9S8
S7
S6
S11
S12
S13
WS
WS
WS
WS
Read Read Read
CLKIN
TM[2:0], SIZ[1:0]
BE
/BWEx, OE