Datasheet

18-14 MCF5407 User’s Manual
Data Transfer Operation
Figure 18-15. Line Read Burst-Inhibited, Fast, External Termination
18.4.7.3 Line Write Bus Cycles
Figure 18-16 shows a line access write with zero wait states. It begins like a basic write bus
cycle with data driven one clock after TS
. The next pipelined burst data is driven a cycle
after the write data is registered (on the rising edge of S6). Each subsequent burst takes a
single cycle. Note that as with the line read example in Figure 18-12, AS
and CSx remain
asserted throughout the burst transfer. This example shows the behavior of the address lines
for both internal and external termination. Note that with external termination, address
lines, like SIZ, TT, and TM, hold the same value for the entire transfer.
Figure 18-16. Line Write Burst (2-1-1-1), Internal/External Termination
A[31:0]
R/W
TT[1:0]
TIP
SIZ[1:0]
TS
D[31:0]
T
A
Line Longword
Basic Fast Fast Fast
A[3:2] = 00 A[3:2] = 01 A[3:2] = 10 A[3:2] = 11
S0 S1 S2 S3 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S7S6
Read Read
Read Read
CLKIN
TM[2:0]
AS
, CSx
BE/BWEx, OE
A[31:0]
SIZ[1:0]
TS
AS, CSx
D[31:0]
T
A
WriteWrite Write Write
S0 S1 S2 S3 S4 S5 S10S9S8S7S6 S11
TM[1:0], TT[1:0]
CLKIN
OE
, BE/BWE
A[31:0]
Internal Termination
External Termination
R/W
, TIP