Datasheet

18-24 MCF5407 User’s Manual
General Operation of External Master Transfers
Figure 18-25. External Master Burst Line Access to 32-Bit Port
Table 18-9 defines the cycles for Figure 18-25.
Table 18-9. Cycles for External Master Burst Line Access to 32-Bit Port
Cycle Definition
C1 The external device is bus master and asserts HOLDREQ, indicating to the MCF5407 to hold all bus
requests. In other words, BD
should not be asserted. The external master drives address, TS, R/W, TT[1:0],
TM[2:0], TIP
, and SIZ[1:0] as inputs to the MCF5407. SIZ[1:0] inputs indicate a line transfer. The MCF5407
is not asserting BR
.
C2–C3 The MCF5407 decodes the external device’s address and control signals to identify the proper chip-select
and byte-enable assertion. The external device negates TS
in C2. Address and R/W are latched in the
MCF5407 on the rising edge of CLKIN in C2. After C2, the address and R/W
are ignored for the rest of the
burst transfer.
C4 On the falling edge of CLKIN, the MCF5407 asserts the appropriate chip select for the external device
access along with the appropriate byte enables.
C5 On the rising edge of CLKIN, data is driven onto the bus by the device selected by CS
. The MCF5407
asserts T
A on the rising edge of CLKIN, indicating the first data transfer is complete.
A[31:0]
R/W
TT[1:0], TM[2:0]
TIP
TS
AS, BR
2
D[31:0]
TA
1
BG, BD
2
External Master
C1 C2 C4 C5 C6 C7C3 C8 C9
CS
1
BE/BWE
1
1
Depending on programming, these signals may or may not be driven by the processor.
C10 C11
2
These signals are driven by the processor for an external master transfer.
CLKIN
SIZ[1:0]
HOLDREQ