Datasheet

Chapter 18. Bus Operation 18-25
General Operation of External Master Transfers
18.9.1 Two-Device Bus Arbitration Protocol (Two-Wire
Mode)
Two-wire mode bus arbitration lets the MCF5407 share the external bus with a single
external bus device without requiring an external bus arbiter. Figure 18-26 shows the
MCF5407 connecting to an external device using the two-wire mode. The MCF5407 BG
input is connected to the HOLDREQ output of the external device; the MCF5407 BD
output is connected to the HOLDACK input of the external device. Because the external
device controls the state of HOLDREQ, it controls when the MCF5407 is granted the bus,
giving the MCF5407 lower priority.
Figure 18-26. MCF5407 Two-Wire Mode Bus Arbitration Interface
When the external device is not using the bus, it negates HOLDREQ, driving BG low and
granting the bus to the MCF5407. When the MCF5407 has an internal bus request pending
and BG
is low, the MCF5407 drives BD low, negating HOLDACK to the external device.
When the external bus device needs the external bus, it asserts HOLDREQ, driving BG
high, requesting the MCF5407 to release the bus. If BG is negated while a bus cycle is in
progress, the MCF5407 releases the bus at the completion of the bus cycle. Note that the
MCF5407 considers the individual transfers of a burst or burst-inhibited access to be a
single bus cycle and does not release the bus until the last transfer of the series completes.
When the bus has been granted to the MCF5407, one of two situations can occur. In the first
case, if the MCF5407 has an internal bus request pending, the MCF5407 asserts BD
to
indicate explicit bus mastership and begins the pending bus cycle by asserting TS
. As
C6–C8 No-wait state data transfers 2–4 occur on the rising edges of CLKIN. TA continues to be asserted indicating
completion of each transfer. TIP
, CSx, and BE/BWE[3:0] are driven.
C9 T
A negates on the rising edge of CLKIN along with external device’s negation of TIP. On the falling edge,
the MCF5407 negates chip select and byte enables, creating an opportunity for another cycle to begin.
Table 18-9. Cycles for External Master Burst Line Access to 32-Bit Port (Continued)
Cycle Definition
BG
BD
BR
HOLDREQ
HOLDACK
External Bus Master
A[31:0]
R/W
SIZ[1:0]
D[31:0]
TS
TA
A[31:0]
R/W
SIZ[1:0]
D[31:0]
TS
TA
To/from external memory and control
MCF5407