Datasheet

18-26 MCF5407 User’s Manual
General Operation of External Master Transfers
shown in Figure 18-25, the MCF5407 continues to assert BD until the completion of the
bus cycle. If BG
is negated by the end of the bus cycle, the MCF5407 negates BD. While
BG
is asserted, BD remains asserted to indicate the MCF5407 is master, and it continuously
drives the address bus, attributes, and control signals.
s
Figure 18-27. Two-Wire Bus Arbitration with Bus Request Asserted
In the second situation, the bus is granted to the MCF5407, but it does not have an internal
bus request pending, so it takes implicit bus mastership. The MCF5407 does not drive the
bus and does not assert BD
if the bus has an implicit master. If an internal bus request is
generated, the MCF5407 assumes explicit bus mastership. If explicit mastership was
assumed because an internal request was generated, the MCF5407 immediately begins an
access and asserts BD
.
In Figure 18-28, the external device is bus master during C1 and C2. During C3 the external
device releases control of the bus by asserting BG
to the MCF5407. At this point, there is
an internal access pending so the MCF5407 asserts BD
during C4 and begins the access.
Thus, the MCF5407 becomes the explicit external bus master. Also during C4, the external
device removes the grant from the MCF5407 by negating BG
. As the current bus master,
the MCF5407 continues to assert BD
until the current transfer completes. Because BG is
negated, the MCF5407 negates BD
during C9 and three-states the external bus, thereby
returning external bus mastership to the external device.
A[31:0], TT[1:0]
R/W
TIP
TS
AS
D[31:0]
TA
BG
BD
External Master
C1 C2 C4 C5 C6 C7C3 C8 C9
MCF5407
CLKIN
SIZ[1:0], TM[2:0]