Datasheet

1-2 MCF5407 User’s Manual
Features
Figure 1-1. MCF5407 Block Diagram
DRAM Controller Chip-Select Module External
Bus Interface
Software
Watchdog
Two
Two UARTs
DMA
I
2
C Module
JTAG
Debug
MAC
V4 COLDFIRE PROCESSOR COMPLEX
2-Kbyte
SRAM1
SYSTEM INTEGRATION MODULE (SIM)
2-Kbyte
SRAM0
16-Kbyte
Instruction
Cache
8-Kbyte
Data
Cache
SRAM Controller
RAMBAR0
RAMBAR1
DIV
Ten-Instruction
FIFO Buffer
Operand Execution
Pipeline (OEP)
Instruction Fetch
Pipeline (IFP)
Branch Logic
8-Entry
Branch
128-Entry
Prediction
Ta bl e
Cache
.
.
.
LIFO Return
Stack
32-Bit Data Bus
4-Entry
Store
Buffer
31 0
Four
32-Bit Address Bus
CCR
General-
Purpose Registers
31 0 31 0
A0–A7 D0–D7
IED
IAG
IC1
IC2
OC2
DS
AG
OC1
DA
EX
Interrupt Controller
Local Memory Local Memory
Instruction Bus
PLL
CLKIN
RSTI
PSTCLK
RSTO
PCLK
CLKIN
Data Bus
÷2
X n
Module
CS[7:0]
888
8
10 ICRs
MBAR
IMR
Channels
General-
Purpose
Timers
(to on-chip
peripherals)
Harvard Cache Controller
ACR2
ACR0
ACR3 ACR1
CACR
CSARs CSCRs CSMRs
IRQ
[1,3,5,7]
4
DRAM Controller
AVR
IPR
IRQPAR
SWIVR
SWSR SYPCR
RSR
System Control PLL Control
PLL
Base Address
MPARK
Bus Master Park
DMR0/1DACR0/1
Addr/Cntrl Mask
DRAM Control
DCR
Parallel Port
PLL
Control Signals
Outputs
Local Memory
Instruction Unit