Datasheet

Chapter 18. Bus Operation 18-33
Reset Operation
The bus arbitration state diagram can be used for the MCF5407 three-wire bus arbitration
protocol to approximate the high-level behavior of the MCF5407. It is assumed that all TS
or AS signals in a system are tied together and each bus device’s BD and BR signals are
connected individually to the external arbiter. The external arbiter must ensure that any
external masters will have released the bus after the next rising edge of CLKIN before
asserting BG
to the MCF5407. The MCF5407 does not monitor external bus master
operation regarding bus arbitration.
NOTE:
The MCF5407 can start a transfer on the rising edge of CLKIN
the cycle after BG
is asserted. The external arbiter should not
assert BG
to the MCF5407 until the previous external master
stops driving the bus or the part may be damaged.
18.10 Reset Operation
The MCF5407 supports two types of reset. Asserting RSTI resets the entire MCF5407. A
software watchdog reset resets everything but the internal PLL module.
Explicit
master
C1 Negated Negated Asserted ———Explicit
master
C2 Negated Negated Negated ———Explicit
master
C3 Negated Negated Negated — Negated — External
device
master
C4 Negated Negated Negated — Yes Negated Explicit
master
C5 Negated Negated Negated — Yes Yes External
device
master
External
master
D1 Negated Negated Negated
1
———External
device
master
D2 Negated Negated Asserted ———Explicit
master
D3 Negated Negated Asserted Negated ——Implicit
master
D4 Negated Negated Asserted Asserted ——Explicit
master
1
Both normal terminations and terminations due to bus errors generate an end of cycle. Bus cycles resulting from
a burst-inhibited transfer are considered part of that original transfer.
Table 18-11. Three-Wire Bus Arbitration Protocol Transition Conditions (Continued)
Current
State
Condition
Label
RSTI
Software
Watchdog
Reset
BG
Bus
Request
Transfer
in
Progress
End of
Cycle
1
Next State