Datasheet

Chapter 18. Bus Operation 18-35
Reset Operation
See Section 17.5.5, “Data/Configuration Pins (D[7:0]).” Motorola recommends that the
data pins be driven rather than using a weak pull-up or pull-down resistor. Table 17-1 lists
the encoding of these pins sampled at reset.
After RSTI
is negated, 32 bits of CPU configuration information are loaded into data
register D0 and 32 bits of internal memory information are loaded in D1. Because D0 and
D1 are uninitialized on previous ColdFire devices, this feature allows users to identify the
MCF5407 through software. Values D1 = 0x0630_0530 and D0 = 0xCF4x_C012 identify
the MCF5407, where x identifies the core revision number (0x1 for the initial device).
18.10.2 Software Watchdog Reset
A software watchdog reset is performed if the executing software does not provide the
correct write data sequence with the enable-control bit set. This reset helps prevent runaway
software or unterminated bus cycles. Figure 18-34 is a functional timing diagram of the
software watchdog reset operation, showing RST
O and bus signal relationships.
Figure 18-34. Software Watchdog Reset Timing
Table 18-12. Data Pin Configuration
Pin Function
D7 Auto-Acknowledge Configuration (AA_CONFIG)
D[6:5] Port Size Configuration (PS_CONFIG[1:0])
D4 Address Configuration (ADDR_CONFIG/D4)
D3 Byte Enable Configuration (BE_CONFIG)
D[2:0] Divide Control (DIVIDE[2:0])
50K CLKIN
RSTO
D[7:0] latched on rising edge of CLKIN
>16 CLKS
CLKIN
RSTI
BCLKO
PSTCLK
D[7:0]
>10 CLKS
Cycle Lock Time