Datasheet

20-4 MCF5407 User’s Manual
Clock Timing Specifications
Figure 20-2. Example Circuit to Control Supply Sequencing
20.2 Clock Timing Specifications
Table 20-4 shows the MCF5407 PLL encodings. Note that they differ from the MCF5307
DIVIDE[1:0] encodings.
Figure 20-3 correlates CLKIN and core clock frequencies for the 3x–6x multipliers.
Figure 20-3. CLKIN-to-Core Clock Frequency Ranges
Table 20-5 lists specifications for the clock timing parameters shown in Figure 20-4 and
Figure 20-5. Motorola recommends that CLKIN be used for the system clock. BCLKO is
provided only for compatibility with slower MCF5307 designs. Regardless of the CLKIN
frequency driven at power-up, CLKIN (and BCLKO) have the same ratio value to the
Table 20-4. Divide Ratio Encodings
D[2:0]/DIVIDE[2:0] Input Clock (MHz) Multiplier Core Clock (MHz) PSTCLK (MHz)
00x–010 Reserved
011 40.0–54.0 3 120.0–162 60.0–81.0
100 25.0–40.5 4 100.0–162 50.0–81.0
101 25.0–32.4 5 125.0–162 67.5–81.0
110 25.0–27.0 6 150.0–162 75.0–81.0
111 Reserved
3.3 V
Regulator
1.8 V
Regulator
EV
cc
IV
cc
, PV
cc
Supply
2
530354045 55
25 27
25 32.4
50 100 110 120 130 140 160
150
125 162
150 170
6x
5x
162
CLKIN (MHz) Core Clock (MHz)
CLKIN Core Clock
40 54 120 162
3x
25 40.5 100 162
4x