Datasheet

Chapter 20. Electrical Specifications 20-5
Clock Timing Specifications
PCLK. Although either signal can be used as a clock reference, CLKIN leaves more room
to meet the bus specifications than BCLKO, which is generated as a phase-aligned signal
to CLKIN.
Figure 20-4 shows timings for the parameters listed in Table 20-5.
Figure 20-4. Clock Timing
Figure 20-5 shows PSTCLK timings for parameters listed in Table 20-5.
Table 20-5. Clock Timing Specification
Num Characteristic
54 MHz CLKIN
Units
Min Max
C1 CLKIN cycle time 18.5 Note
1
1
The PLL low-frequency limit depends on the clock divide ratio chosen. See Table 20-4.
nS
C2 CLKIN rise time (0.5V to 2.4 V) — 2nS
C3 CLKIN fall time (2.4V to 0.5 V) — 2nS
C4 CLKIN duty cycle (at 1.5 V) 40 60 %
C5 PSTCLK cycle time 12.3 Note
1
nS
C6 PSTCLK duty cycle (at 1.5 V) 40 60 %
C7 BCLKO cycle time 18.5 Note
1
nS
C8 BCLKO duty cycle (at 1.5 V) 45 55 %
C9 CLKIN to BCLKO -1.5 1.5 nS
CLKIN
BCLKO
C1
C4 C4
C3
C2
C7
C8 C8
C9
Note: Input and output AC timing specifications are measured to CLKIN with a 50-pF load capacitance (not
including pin capacitance).