Datasheet

20-10 MCF5407 User’s Manual
Input/Output AC Timing Specifications
Figure 20-8. SDRAM Write Cycle with EDGESEL Tied to Buffered CLKIN
Figure 20-9 shows an SDRAM read cycle with EDGESEL tied high.
A[31:0]
TS
SRAS
SCAS
1
D[31:0]
ACTV PALL
NOP
RAS
WRITE
Row Column
EDGESEL
DRAMW
CAS
B16
B15
B15
B16
B16
B16
0
1 2 3 4 5 6 7 8 9 10 11 12
CLKIN
B15
1
DACR[CASL] = 2
B6
NOP