Datasheet

Chapter 20. Electrical Specifications 20-11
Input/Output AC Timing Specifications
Figure 20-9. SDRAM Read Cycle with EDGESEL Tied High
Figure 20-10 shows an SDRAM write cycle with EDGESEL tied high.
A[31:0]
TS
SRAS
D[31:0]
ACTV NOP PALLNOP
RAS
READ
Row Column
CLKIN
0
DRAMW
CAS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
B11
B10
B10
B11
B2
B1
B11
B11
1
DACR[CASL] = 2
SCAS
1
NOP