Datasheet

Chapter 1. Overview 1-5
MCF5407 Features
• Two, 2-Kbyte SRAMs
— Programmable location anywhere within 4-Gbyte linear address space
— Higher core-frequency operation
— Pipelined, single-cycle access to critical code or data
— Each block mappable to either the instruction or data operand bus
• DMA controller
— Four fully programmable channels: two support external requests and external
acknowledges
— Dual-address and single-address transfer support with 8-, 16-, and 32-bit data
capability
— Source/destination address pointers that can increment or remain constant
— 24-bit transfer counter per channel
— Operand packing and unpacking supported
— Auto-alignment transfers supported for efficient block movement
— Bursting and cycle steal support
— Two-bus-clock internal access
— Automatic DMA transfers from on-chip UARTs using internal interrupts
• DRAM controller
— Synchronous DRAM (SDRAM), extended-data-out (EDO) DRAM, and fast
page mode support
— Up to 512 Mbytes of DRAM
— Programmable timer provides CAS-before-RAS refresh for asynchronous
DRAMs
— Support for two separate memory blocks
•Two UARTs
— One UART offers synchronous mode with expanded buffers for soft modem
support
— Full-duplex operation
— Programmable clock
— Modem control signals available (CTS
, RTS)
— Processor-interrupt capability
• Dual 16-bit general-purpose multiple-mode timers
— 8-bit prescaler
— Timer input and output pins
— Processor-interrupt capability
— Up to 18.5-nS resolution at 54 MHz