Datasheet

20-14 MCF5407 User’s Manual
Input/Output AC Timing Specifications
Figure 20-12. SDRAM Write Cycle with EDGESEL Tied Low
Figure 20-13 shows AC timing showing high impedance.
Figure 20-13. AC Output Timing—High Impedance
A[31:0]
TS
SRAS
SCAS
1
D[31:0]
ACTV PALLNOP
RAS
WRITE
Row Column
CLKIN
DRAMW
CAS
B14
B13
B13
B14
B14
B14
0
1 2 3 4 5 6 7 8 9 10 11 12
B13
1
DACR[CASL] = 2
NOP
H1 H2
HIZ
OUTPUTS