Datasheet

20-16 MCF5407 User’s Manual
Debug AC Timing Specifications
20.5 Debug AC Timing Specifications
Table 20-9 lists specifications for the debug AC timing parameters shown in Figure 20-16.
Figure 20-15 shows real-time trace timing for the values in Table 20-9.
Figure 20-15. Real-Time Trace AC Timing
Figure 20-16 shows BDM serial port AC timing for the values in Table 20-9.
Figure 20-16. BDM Serial Port AC Timing
Table 20-9. Debug AC Timing Specification
Num Characteristic
54 MHz CLKIN
Units
Min Max
D1 PSTDDATA to PSTCLK setup 4.5 — nS
D2 PSTCLK to PSTDDATA hold 4.5 — nS
D3 DSI-to-DSCLK setup 1 — PSTCLKs
D4
1
1
DSCLK and DSI are synchronized internally. D4 is measured from the
synchronized DSCLK input relative to the rising edge of PSTCLK.
DSCLK-to-DSO hold 4 — PSTCLKs
D5 DSCLK cycle time 5 — PSTCLKs
PSTCLK
PSTDDATA[7:0]
D2
D1
DSI
DSO
Current Next
PSTCLK
Past Current
DSCLK
D3
D4
D5