Datasheet

A-6 MCF5407 User’s Manual
Timing Differences
The UART module interfaces directly to the CPU as shown in Figure A-2. The UART
module consists of the following major functional areas:
• Serial communication channel
• 16-bit timer for baud-rate generation
• Internal channel control logic
• Interrupt control logic
Figure A-2. Simplified Block Diagram
In addition, UART1 has been enhanced to provide a CODEC interface for soft modem
support. UART1 can be programmed to provide any one of the following functions:
• The original UART (identical to UART0)
• Three modem modes, (see Section 14.5.2.2, “Transmitter in Modem Mode
(UART1) for more details)”:
— An 8-bit CODEC interface
— A 16-bit CODEC interface
— An audio CODEC 97 (AC97) digital interface controller
A.6 Timing Differences
This section explains timing relationships within phase-locked loop registers.
A.6.1 Phase-Locked Loop (PLL)
The PLL for the MCF5407 is enhanced to support faster processor clock (PCLK)
frequencies. The MCF5307 supports PCLK frequencies of 66.7 and 90 MHz with a clock
input (CLKIN) of 1/2 PCLK. The MCF5407 offers a larger range of clock input ratios and
a higher performance processor clock. For more details see Section 7.1.1, “PLL:PCLK
Ratios” and Chapter 20, “Electrical Specifications”.
The MCF5407 PLL module is shown in Figure A-3.
Serial
Interrupt Control
Logic
CTS
RTS
RxD
TxD
CLKIN
or
External clock (TIN)
Internal Channel
Control Logic
16-Bit Timer for
Baud-Rate
Communications
Channel
Generation
System Integration
Module (SIM)
Interrupt
Controller
UART