Datasheet

Appendix A. Migrating from the ColdFire MCF5307 to the MCF5407 A-11
Revision C Debug
frame, shown in Figure A-4.
As part of the Debug C enhancement, the operation of the debug interrupt is modified as
follows:
• The occurrence of the breakpoint trigger, configured to generate a debug interrupt,
is treated exactly as before. The debug interrupt is treated as a higher priority
exception relative to the normal interrupt requests encoded on the interrupt priority
input signals.
• At the appropriate sample point, the processor initiates debug interrupt exception
processing. This event is signaled externally by the generation of a unique PST value
(PST = 0xD) asserted for multiple cycles. The processor sets the emulator mode
state bit as part of this processing.
• All normal interrupt requests are evaluated and sampled once per instruction during
the debug interrupt service routine. If an exception is detected, the processor takes
the following steps:
1. In response to the new exception, the processor saves a copy of the current value of
the emulator mode state bit and then exits emulator mode by clearing the actual
state.
2. The new exception stack frame sets bit 1 of the fault status field, using the saved
emulator mode bit, indicating that execution while the processor is in emulator mode
was interrupted. This corresponds to bit [17] of the longword at the top of the system
stack.
3. Control is passed to the appropriate exception handler.
4. When the exception handler is complete, a Return From Exception (RTE)
instruction is executed. During the processing of the RTE, the FS1 bit is reloaded
from the system stack. If FS1 = 1, the processor sets the emulator mode state and
resumes execution of the original debug interrupt service routine. This is signaled
externally by the generation of the PST value that originally identified the
occurrence of a debug interrupt exception, that is, PST = 0xD.
Implementation of this revised debug interrupt handling fully supports the servicing of any
number of normal interrupt requests while in a debug interrupt service routine. The
emulator mode state bit is essentially changed to a program-visible value, stored into
memory when the exception stack frame is created, and loaded from memory by the RTE
instruction.
31 28 27 26 25 18 17 16 15 0
A7→ Format FS[3–2] Vector[7–0] FS[1–0] Status Register
+ 0x04 Program counter[31:0]
Figure A-4. Exception Stack Frame Form