Datasheet

Appendix B. List of Memory Maps B-1
Appendix B
List of Memory Maps
Table B-1. SIM Registers
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]
0x000 Reset status register
(RSR) [p. 6-5]
System protection
control register
(SYPCR) [p. 6-8]
Software watchdog
interrupt vector register
(SWIVR) [p. 6-9]
Software watchdog
service register (SWSR)
[p. 6-9]
0x004 Pin assignment register (PAR) [p. 6-10] Interrupt port
assignment register
(IRQPAR) [p. 9-7]
Reserved
0x008 PLL control (PLLCR)
[p. 7-3]
Reserved
0x00C Default bus master park
register (MPARK)
[p. 6-11]
Reserved
0x010–
0x03C
Reserved
Table B-2. Interrupt Controller Registers
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]
Interrupt Registers [p. 9-3]
0x040 Interrupt pending register (IPR) [p. 9-6]
0x044 Interrupt mask register (IMR) [p. 9-6]
0x048 Reserved Autovector register
(AVR) [p. 9-5]
Interrupt Control Registers (ICRs) [p. 9-3]
0x04C Software watchdog
timer (ICR0) [p. 6-6]
Timer0 (ICR1) [p. 9-2] Timer1 (ICR2) [p. 9-3] I
2
C (ICR3) [p. 9-3]
0x050 UART0 (ICR4) [p. 9-3] UART1 (ICR5) [p. 9-3] DMA0 (ICR6) [p. 9-3] DMA1 (ICR7) [p. 9-3]
0x054 DMA2 (ICR8) [p. 9-3] DMA3 (ICR9) [p. 9-3] Reserved