Datasheet

Chapter 1. Overview 1-11
ColdFire Module Description
and remote loopback modes allow testing of UART connections. The programmable
UARTs can interrupt the CPU on various normal or error-condition events.
1.3.6 Timer Module
The timer module includes two general-purpose timers, each of which contains a
free-running 16-bit timer for use in any of three modes. One mode captures the timer value
with an external event. Another mode triggers an external signal or interrupts the CPU when
the timer reaches a set value, while a third mode counts external events.
The timer unit has an 8-bit prescaler that allows programming of the clock input frequency,
which is derived from the system bus cycle or an external clock input pin (TIN). The
programmable timer-output pin generates either an active-low pulse or toggles the output.
1.3.7 I
2
C Module
The I
2
C interface is a two-wire, bidirectional serial bus used for quick data exchanges
between devices. The I
2
C minimizes the interconnection between devices in the end system
and is best suited for applications that need occasional bursts of rapid communication over
short distances among several devices. The I
2
C can operate in master, slave, or
multiple-master modes.
1.3.8 System Interface
The MCF5407 processor provides a direct interface to 8-, 16-, and 32-bit FLASH, SRAM,
ROM, and peripheral devices through the use of fully programmable chip selects and write
enables. Support for burst ROMs is also included. Through the on-chip PLL, users can
input a slower clock (25 to 54 MHz) that is internally multiplied to create the faster
processor clock (100 to 162 MHz).
1.3.8.1 External Bus Interface
The bus interface controller transfers information between the ColdFire core or DMA and
memory, peripherals, or other devices on the external bus. The external bus interface
provides up to 32 bits of address bus space, a 32-bit data bus, and all associated control
signals. This interface implements an extended synchronous protocol that supports bursting
operations.
Simple two-wire request/acknowledge bus arbitration between the MCF5407 processor
and another bus master, such as an external DMA device, is glueless with arbitration logic
internal to the MCF5407 processor. Multiple-master arbitration is also available with some
simple external arbitration logic.
1.3.8.2 Chip Selects
Eight fully programmable chip select outputs support the use of external memory and
peripheral circuits with user-defined wait-state insertion. These signals interface to 8-, 16-,