Datasheet

Chapter 1. Overview 1-17
Programming Model, Addressing Modes, and Instruction Set
operation sizes, and assembler syntax. For two-operand instructions, the first operand is
generally the source operand and the second is the destination.
Because the ColdFire architecture provides an upgrade path for 68K customers, its
instruction set supports most of the common 68K opcodes. A majority of the instructions
are binary compatible or optimized 68K opcodes. This feature, when coupled with the code
conversion tools from third-party developers, generally minimizes software porting issues
for customers with 68K applications.
The following list summarizes new and enhanced instructions of Revision B ISA:
• New instructions:
— INTOUCH loads blocks of instructions to be locked in the instruction cache.
— MOV3Q.L moves 3-bit immediate data to destination location.
— MVS.{B,W} sign-extends the source operand and moves it to destination
register.
— MVZ.{B,W} zero-fills the source operand and moves it to destination register.
— SATS.L updates bit 31 of destination register depending on CCR overflow bit.
— TAS.B tests and set byte operand being addressed.
• Enhancements to existing Revision A instructions:
— Longword support for branch instructions (Bcc, BRA, BSR)
— Byte and word support for compare instructions (CMP, CMPI)
— Byte and longword support for MOVE.x where the source is of type #<data> and
the destination is of type d16(Ax); that is, move.b #<data>, d16(Ax)