Datasheet

Part I. MCF5407 Processor Core I-xix

Part I

MCF5407 Processor Core

Intended Audience

Part I is intended for system designers who need a general understanding of the

functionality supported by the MCF5407. It also describes the operation of the MCF5407

ColdFire core and its multiply/accumulate (MAC) execution unit. It describes the

programming and exception models, Harvard memory implementation, and debug module.

Contents

• Chapter 2, “ColdFire Core,” provides an overview of the microprocessor core of the

MCF5407. The chapter begins with a description of enhancements from the V3

ColdFire core, and then fully describes the V4 programming model as it is

implemented on the MCF5407. It also includes a full description of exception

handling, data formats, an instruction set summary, and a table of instruction

timings.

• Chapter 3, “Hardware Multiply/Accumulate (MAC) Unit,” describes the MCF5407

multiply/accumulate unit, which executes integer multiply, multiply-accumulate,

and miscellaneous register instructions. The MAC is integrated into the operand

execution pipeline (OEP).

• Chapter 4, “Local Memory.” This chapter describes the MCF5407 implementation

of the ColdFire V4 local memory speciﬁcation. It consists of the two following

major sections.

— Section 4.2, “SRAM Overview,” describes the MCF5407 on-chip static RAM

(SRAM) implementation. It covers general operations, conﬁguration, and

initialization. It also provides information and examples showing how to

minimize power consumption when using the SRAM.

— Section 4.7, “Cache Overview,” describes the MCF5407 cache implementation,

including organization, conﬁguration, and coherency. It describes cache

operations and how the cache interacts with other memory structures.