Datasheet

2-12 MCF5407 User’s Manual
Programming Model
2.2.2.2 Vector Base Register (VBR)
The VBR holds the base address of the exception vector table in memory. The displacement
of an exception vector is added to the value in this register to access the vector table.
VBR[19–0] are not implemented and are assumed to be zero, forcing the vector table to be
aligned on a 0-modulo-1-Mbyte boundary.
2.2.2.3 Cache Control Register (CACR)
The CACR controls operation of both the instruction and data cache memory. It includes
bits for enabling, freezing, and invalidating cache contents. It also includes bits for defining
the default cache mode and write-protect fields. See Section 4.10.1, “Cache Control
Register (CACR).”
2.2.2.4 Access Control Registers (ACR0–ACR3)
The access control registers (ACR0–ACR3) define attributes for four user-defined memory
regions. ACR0 and ACR1 control data memory space and ACR2 and ACR3 control
instruction memory space. Attributes include definition of cache mode, write protect and
buffer write enables. See Section 4.10.2, “Access Control Registers (ACR0–ACR3).”
2.2.2.5 RAM Base Address Registers (RAMBAR0 and RAMBAR1)
The RAMBAR registers determine the base address location of the internal SRAM
modules and indicate the types of references mapped to each. Each RAMBAR includes a
base address, write-protect bit, address space mask bits, and an enable. The RAM base
address must be aligned on a 0-module-2-Kbyte boundary. See Section 4.4.1, “SRAM Base
Address Registers (RAMBAR0/RAMBAR1).”
2.2.2.6 Module Base Address Register (MBAR)
The module base address register (MBAR) defines the logical base address for the
memory-mapped space containing the control registers for the on-chip peripherals. See
Section 6.2.2, “Module Base Address Register (MBAR).”
313029282726252423222120191817161514131211109876543210
Field Exception vector table base address —
Reset 0000_0000_0000_0000_0000_0000_0000_0000
R/W Written from a BDM serial command or from the CPU using the MOVEC instruction. VBR can be read from
the debug module only. The upper 12 bits are returned, the low-order 20 bits are undefined.
Rc[11–0] 0x801
Figure 2-6. Vector Base Register (VBR)