Datasheet
viii
MCF5407 User’s Manual
CONTENTS
Paragraph
Number
Title
Page
Number
4.9.2 Cache-Inhibited Accesses ............................................................................. 4-14
4.9.3 Cache Protocol.............................................................................................. 4-15
4.9.3.1 Read Miss ................................................................................................. 4-16
4.9.3.2 Write Miss (Data Cache Only) ................................................................. 4-16
4.9.3.3 Read Hit .................................................................................................... 4-16
4.9.3.4 Write Hit (Data Cache Only).................................................................... 4-17
4.9.4 Cache Coherency (Data Cache Only)........................................................... 4-17
4.9.5 Memory Accesses for Cache Maintenance................................................... 4-17
4.9.5.1 Cache Filling............................................................................................. 4-17
4.9.5.2 Cache Pushes ............................................................................................ 4-18
4.9.5.2.1 Push and Store Buffers ......................................................................... 4-18
4.9.5.2.2 Push and Store Buffer Bus Operation................................................... 4-18
4.9.6 Cache Locking .............................................................................................. 4-19
4.10 Cache Registers................................................................................................. 4-21
4.10.1 Cache Control Register (CACR) .................................................................. 4-21
4.10.2 Access Control Registers (ACR0–ACR3).................................................... 4-23
4.11 Cache Management........................................................................................... 4-24
4.12 Cache Operation Summary ............................................................................... 4-27
4.12.1 Instruction Cache State Transitions .............................................................. 4-27
4.12.2 Data Cache State Transitions........................................................................ 4-28
4.13 Cache Initialization Code.................................................................................. 4-32
Chapter 5
Debug Support
5.1 Overview............................................................................................................. 5-1
5.2 Signal Descriptions ............................................................................................. 5-2
5.2.1 Processor Status/Debug Data (PSTDDATA[7:0]) ......................................... 5-3
5.3 Real-Time Trace Support.................................................................................... 5-4
5.3.1 Begin Execution of Taken Branch (PST = 0x5) ............................................. 5-6
5.3.2 Processor Stopped or Breakpoint State Change (PST = 0xE) ........................ 5-7
5.3.3 Processor Halted (PST = 0xF) ........................................................................ 5-7
5.4 Programming Model ........................................................................................... 5-8
5.4.1 Address Attribute Trigger Registers (AATR, AATR1)................................ 5-10
5.4.2 Address Breakpoint Registers (ABLR/ABLR1, ABHR/ABHR1) ............. 5-12
5.4.3 BDM Address Attribute Register (BAAR)................................................... 5-12
5.4.4 Configuration/Status Register (CSR)............................................................ 5-13
5.4.5 Data Breakpoint/Mask Registers (DBR/DBR1, DBMR/DBMR1) ............ 5-15
5.4.6 Program Counter Breakpoint/Mask Registers
(PBR, PBR1, PBR2, PBR3, PBMR) ........................................................ 5-16
5.4.7 Trigger Definition Register (TDR) ............................................................... 5-18
5.4.8 Extended Trigger Definition Register (XTDR) ............................................ 5-19