Datasheet

2-14 MCF5407 User’s Manual
Organization of Data in Registers
operands are sign-extended to 32 bits and then used in the operation with anaddress register
destination. When an address register is a destination, the entire register is affected,
regardless of the operation size. Figure 2-8 shows integer formats for address registers.
The size of control registers varies according to function. Some have undefined bits
reserved for future definition by Motorola. Those particular bits read as zeros and must be
written as zeros for future compatibility.
All operations to the SR and CCR are word-size operations. For all CCR operations, the
upper byte is read as all zeros and is ignored when written, regardless of privilege mode.
2.4.2 Organization of Integer Data Formats in Memory
All ColdFire processors use a big-endian addressing scheme. The byte-addressable
organization of memory allows lower addresses to correspond to higher order bytes. The
address N of a longword data item corresponds to the address of the high-order word. The
lower order word is located at address N + 2. The address N of a word data item corresponds
to the address of the high-order byte. The lower order byte is located at address N + 1. This
organization is shown in Figure 2-9.
31 16 15 0
Sign-Extended 16-Bit Address Operand
31 0
Full 32-Bit Address Operand
Figure 2-8. Organization of Integer Data Formats in Address Registers
31 23 15 7 0
Longword 0x0000_0000
Word 0x0000_0000 Word 0x0000_0002
Byte 0x0000_0000 Byte 0x0000_0001 Byte 0x0000_0002 Byte 0x0000_0003
Longword 0x0000_0004
Word 0x0000_0004 Word 0x0000_0006
Byte 0x0000_0004 Byte 0x0000_0005 Byte 0x0000_0006 Byte 0x0000_0007
.
.
.
Longword 0xFFFF_FFFC
Word 0xFFFF_FFFC Word 0xFFFF_FFFE
Byte 0xFFFF_FFFC Byte 0xFFFF_FFFD Byte 0xFFFF_FFFE Byte 0xFFFF_FFFF
Figure 2-9. Memory Operand Addressing