Datasheet
Chapter 2. ColdFire Core 2-23
Execution Timings
2.7 Execution Timings
The timing data presented in this section assumes the following:
• Execution times are shown for individual instructions without assumptions
regarding the OEP’s ability to dispatch multiple instructions at a time. For sequences
where instruction pairs are issued, the execution time of the two instructions is
defined by the execution time of the first instruction; that is, the second instruction
effectively executes in zero cycles.
• The OEP is loaded with the opword and all required extension words at the
beginning of each instruction execution. This implies that the OEP spends no time
waiting for the IFP to supply opwords and/or extension words.
• The OEP experiences no sequence-related pipeline stalls. For the MCF5407, the
most common example of such a stall occurs when a register is modified in the EX
compute engine and a subsequent instruction generating an address uses the
previously modified register. The second instruction stalls in the OEP until the
register is updated by the previous instruction. For example:
muls.l #<data>,d0
move.l (a0,d0.l*4),d1
Table 2-9. Supervisor-Level Instruction Set Summary
Instruction Operand Syntax Operand Size Operation
CPUSHL (An) Unsized Invalidate instruction cache line
Push and invalidate data cache line
Push data cache line and invalidate (I,D)-cache lines
HALT
1
1
The HALT instruction can be configured to allow user-mode execution by setting CSR[UHE].
none Unsized Enter halted state
INTOUCH (Ay) Unsized Touch instruction space at address Ay
MOVE from SR SR, Dx .W SR → Dx
MOVE to SR Dy,SR
#<data>,SR
.W Source → SR
MOVEC Ry,Rc .L Ry → Rc
Rc Register Definition
0x002 Cache control register (CACR)
0x004 Access control register 0 (ACR0)
0x005 Access control register 1 (ACR1)
0x006 Access control register 2 (ACR2)
0x007 Access control register 3 (ACR3)
0x801 Vector base register (VBR)
0xC04 RAM base address register 0 (RAMBAR0)
0xC05 RAM base address register 1 (RAMBAR1)
RTE None Unsized (SP+2) → SR; SP+4 → SP; (SP) → PC; SP + formatfield SP
STOP #<data> .W Immediate data → SR; enter stopped state
WDEBUG <ea-2>y .L <ea-2>y → debug module