Datasheet

CONTENTS
Paragraph
Number
Title
Page
Number
Contents ix
5.4.9 Resulting Set of Possible Trigger Combinations.......................................... 5-21
5.5 Background Debug Mode (BDM) .................................................................... 5-22
5.5.1 CPU Halt....................................................................................................... 5-22
5.5.2 BDM Serial Interface.................................................................................... 5-24
5.5.2.1 Receive Packet Format ............................................................................. 5-25
5.5.2.2 Transmit Packet Format............................................................................ 5-26
5.5.3 BDM Command Set...................................................................................... 5-26
5.5.3.1 ColdFire BDM Command Format............................................................ 5-27
5.5.3.1.1 Extension Words as Required............................................................... 5-28
5.5.3.2 Command Sequence Diagrams................................................................. 5-28
5.5.3.3 Command Set Descriptions ...................................................................... 5-30
5.5.3.3.1 Read A/D Register (
RAREG / RDREG ) ..................................................... 5-30
5.5.3.3.2 Write A/D Register (
WAREG / WDREG )................................................... 5-31
5.5.3.3.3 Read Memory Location (
READ )............................................................ 5-32
5.5.3.3.4 Write Memory Location (
WRITE ) ......................................................... 5-33
5.5.3.3.5 Dump Memory Block (
DUMP ) .............................................................. 5-35
5.5.3.3.6 Fill Memory Block (
FILL )..................................................................... 5-37
5.5.3.3.7 Resume Execution (
GO )........................................................................ 5-39
5.5.3.3.8 No Operation (
NOP ) .............................................................................. 5-40
5.5.3.3.9 Synchronize PC to the PSTDDATA Lines (
SYNC _ PC ) ........................ 5-41
5.5.3.3.10 Read Control Register (
RCREG ) ............................................................ 5-42
5.5.3.3.11 Write Control Register (
WCREG ) .......................................................... 5-43
5.5.3.3.12 Read Debug Module Register (
RDMREG ) ............................................. 5-44
5.5.3.3.13 Write Debug Module Register (
WDMREG ) ........................................... 5-45
5.6 Real-Time Debug Support ................................................................................ 5-45
5.6.1 Theory of Operation...................................................................................... 5-46
5.6.1.1 Emulator Mode ......................................................................................... 5-48
5.6.2 Concurrent BDM and Processor Operation .................................................. 5-48
5.7 Motorola-Recommended BDM Pinout............................................................. 5-49
5.8 Debug C Definition of PSTDDATA Outputs................................................... 5-49
5.8.1 User Instruction Set ...................................................................................... 5-50
5.8.2 Supervisor Instruction Set............................................................................. 5-53
Part II
System Integration Module (SIM)
Chapter 6
SIM Overview
6.1 Features............................................................................................................... 6-1
6.2 Programming Model ........................................................................................... 6-3
6.2.1 SIM Register Memory Map............................................................................ 6-3