Datasheet

2-30 MCF5407 User’s Manual
Execution Timings
2.7.5 Branch Instruction Execution Times
Table 2-17 shows general branch instruction timing.
Table 2-18 shows timing for Bcc instructions.
unlk Ax 1(1/0) — — — — — — —
wddata.
{b,w,l}
<ea> — 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) —
wdebug.l <ea> — 15(2/0) — — 15(2/0) — — —
1
n is the number of registers moved by the MOVEM opcode
2
The execution time for STOP is the time required until the processor begins sampling continuously for interrupts.
Table 2-17. Branch Instruction Execution Times
Opcode <ea>
Effective Address
Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>
bra ————1(0/1)
1
1
Assumes branch acceleration.
———
bsr — — — — 1(0/1)
1
———
jmp <ea> — 5(0/0) — — 5(0/0) 6(0/0) 1(0/0)
1
—
jsr <ea> — 5(0/1) — — 5(0/1) 6(0/1) 1(0/1)
1
—
rte — — 15(2/0) — — — — —
rts — — 2(1/0)
2
9(1/0)
3
8(1/0)
4
2
If predicted correctly by the hardware return stack.
3
If mispredicted by the hardware return stack.
4
If not predicted by the hardware return stack.
—————
Table 2-18. Bcc Instruction Execution Times
Opcode
Branch Cache Correctly
Predicts Taken
Prediction Table Correctly
Predicts Taken
Predicted
Correctly as
Not Taken
Predicted Incorrectly
bcc 0(0/0) 1(0/0) 1(0/0) 8(0/0)
Table 2-16. Miscellaneous Instruction Execution Times (Continued)
Opcode <ea>
Effective Address
Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>