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Table Of Contents

MCF5441x ColdFire Microprocessor Data Sheet

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: MCF54418

Rev. 8, 06/2012

This document contains information on a new product. Specifications and information herein

are subject to change without notice.

MCF5441x

MAPBGA–256

17mm x 17mm

MAPBGA–196

12 mm x 12 mm

• Version 4 ColdFire Core with EMAC and

MMU

• Up to 385 Dhrystone 2.1 MIPS @ 250 MHz

• 8 KB instruction cache and 8 KB data cache

• 64 KB internal SRAM dual-ported to

processor local bus and other crossbar switch

masters

• System boot from NOR, NAND, SPI flash,

EEPROM, or FRAM

• Crossbar switch technology (XBS) for

concurrent access to peripherals or RAM

from multiple bus masters

• 64-channel DMA controller

• SDRAM controller supporting full-speed

operation from a single x8 DDR2 component

up to 250 MHz

• 32-bit FlexBus external memory interface for

RAM, ROM, MRAM, and programmable

logic

• USB 2.0 host controller

• USB 2.0 host/device/On-the-Go controller

• 8-bit single data rate ULPI port usable by the

dedicated USB host module or the USB

host/device/OTG module

• Dual 10/100 Ethernet MACs with hardware

CRC checking/generation, IEEE 1588-2002

support, and optional Ethernet switch

• CPU direct-attached hardware accelerator for

DES, 3DES, AES, MD5, SHA-1, and

SHA-256 algorithms

• Random number generator

• Enhanced Secure Digital host controller for

SD, SDHC, SDIO, MMC, and MMCplus

cards

• Two ISO7816 smart card interfaces

•Two FlexCAN modules

•Six I

C bus interfaces with DMA support in

master mode

• Two synchronous serial interfaces

• Four 32-bit timers with DMA support

• Four programmable interrupt timers

• 8-channel, 16-bit motor control PWM timer

• Dual 12-bit ADCs with shared input channels

and multiple conversion trigger sources

• Dual 12-bit DACs with DMA support

• 1-wire module with DMA support

• NAND flash controller

• Real-time clock with 32-kHz oscillator, 2 KB

standby SRAM, and battery backup supply

input

• Up to four DMA-supported serial peripheral

interfaces (DSPI)

• Up to ten UARTs with single-wire mode

support

• Up to five external IRQ interrupts and 2

external DMA request/acknowledge pairs

• Up to 16 processor local bus Rapid GPIO pins

• Up to 87 standard GPIO pins

MCF5441x ColdFire

Microprocessor Data Sheet

Summary of content (61 pages)

PAGE 1
Freescale Semiconductor Data Sheet: Technical Data Document Number: MCF54418 Rev. 8, 06/2012 MCF5441x MAPBGA–256 17mm x 17mm MAPBGA–196 12 mm x 12 mm MCF5441x ColdFire Microprocessor Data Sheet • • • • • • • • • • • • • • • Version 4 ColdFire Core with EMAC and MMU Up to 385 Dhrystone 2.
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Table of Contents 1 2 3 4 MCF5441x family comparison . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Hardware design considerations . . . . . . . . . . . . . . . . . . . . . . .5 2.1 Power filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.2 Supply voltage sequencing . . . . . . . . . . . . . . . . . . . . . . .7 2.2.1 Power-up sequence . . . . . . . . . . . . . . . . . . . . . . .8 2.2.
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MCF5441x JTAG Version 4 ColdFire Core 8 KB Instruction Cache 8 KB Data Cache EMAC BDM Hardware Divide CAU MMU RGPIO 64 KB SRAM PLL Oscillator PLL 2 Ethernet Controllers eDMA USB Host L2 Switch Serial Boot Facility eSDHC USB OTG NAND Flash Controller Crossbar Switch (XBS) Peripheral Bus Controller 1 Peripheral Bus Controller 0 FlexBus Smart Card ADC 2 DACs 1 Wire mcPWM RTC & kHz Oscillator RNG EPORT 2 DSPIs 4 I2Cs GPIO 6 UARTs 2 SSIs 2 FlexCANs 2 I2Cs 2 DSPIs 3 INTCs 4 UAR
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MCF5441x family comparison 1 MCF5441x family comparison Table 1. MCF5441x family configurations Module MCF54410 MCF54415 MCF54416 MCF54417 MCF54418 Version 4 ColdFire core with EMAC (enhanced multiply-accumulate unit) and MMU (memory management unit)      Cryptography acceleration unit (CAU) — —  —  Core (system) and SDRAM clock up to 250 MHz Peripheral clock (Core clock  2) up to 125 MHz External bus (FlexBus) clock up to 100 MHz Performance (Dhrystone 2.
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Hardware design considerations Table 1.
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Hardware design considerations 10  VDD_OSC_A_PLL EVDD Pin 1 µF 0.1 µF VSS_OSC 100 MHz GND Figure 1. Oscillator/PLL/DAC power filter Figure 2 shows an example for isolating the ADC power supply from the I/O supply (EVDD) and ground. Note that in this power supply the 10  resistor is replaced by a 0  resistor. This will reduce the IR drop into the ADC, limiting additional gain error. 0 Board 3.3 V supply VDDA_ADC 10 µF 0.1 µF GND Figure 2.
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Hardware design considerations Figure 5 shows an example for bypassing the FlexBus power supply for the MPU. This bypass should be applied to as many FB_VDD signals as routing allows. Each one should be placed as close to the ball as possible. Board 1.8–3.3 V supply FB_VDD 1 µF 0.1 µF GND Figure 5. FB_VDD power filter 2.
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Hardware design considerations 2.2.1 Power-up sequence If EVDD/FBVDD/SDVDD are powered up with the IVDD at 0 V, the sense circuits in the I/O pads cause all pad output drivers connected to the EVDD/FBVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/FBVDD/SDVDD powers up before IVDD must power up. IVDD should not lead the EVDD, FBVDD, or SDVDD by more than 0.4 V during power ramp-up, or there will be high current in the internal ESD protection diodes.
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Pin assignments and reset states Table 3. Estimated power consumption specifications (continued) Characteristic Symbol External I/O pad operating supply current (nominal 3.3 V) EVDD USB operating supply current (nominal 3.3 V) VDD_USBO, VDD_USBH ADC operating supply current (nominal 3.3 V) Speed mode 00 Speed mode 01 VDDA_ADC DAC operating supply current (nominal 3.
PAGE 10
Pin assignments and reset states Table 4. Special-case default signal functionality Pin Default signal FB_CLK, FB_OE, FB_R/W, FB_BE/BWE[1:0], FB_CS[5:4] FB_CLK, FB_OE, FB_R/W, FB_BE/BWE[1:0], FB_CS[5:4] FB_ALE FB_ALE or FB_TS (depending on RCON[3]) FB_BE/BWE3 Boot from NFC, NF_ALE. Otherwise, FB_BE/BWE3. FB_BE/BWE2 Boot from NFC, NF_CLE. Otherwise, FB_BE/BWE2. FB_CS1 Boot from NFC, NFC_CE. Otherwise, GPIO. FB_CS0 Boot from FlexBus, FB_CS0. Otherwise, GPIO. FB_TA Boot from NFC, NFC_R/B.
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Pin assignments and reset states Signal name GPIO Alternate 1 Alternate 2 Pullup (U)1 Pulldown (D) Direction2 Voltage domain Pad type3 196 MAPBGA 256 MAPBGA Table 5.
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Pin assignments and reset states Pullup (U)1 Pulldown (D) Direction2 Voltage domain Pad type3 196 MAPBGA 256 MAPBGA Table 5.
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Pin assignments and reset states 196 MAPBGA 256 MAPBGA Alternate 2 Pad type3 Alternate 1 Voltage domain GPIO Direction2 Signal name Pullup (U)1 Pulldown (D) Table 5.
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Pin assignments and reset states Signal name GPIO Alternate 1 Alternate 2 Pullup (U)1 Pulldown (D) Direction2 Voltage domain Pad type3 196 MAPBGA 256 MAPBGA Table 5.
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Pin assignments and reset states Voltage domain Pad type3 196 MAPBGA 256 MAPBGA SDHC_DAT3 PF2 PWM_A1 DSPI1_PCS0 — I/O EVDD msr — B13 SDHC_DAT2 PF1 PWM_B1 DSPI1_PCS2 — I/O EVDD msr — E14 SDHC_DAT1 PF0 PWM_A2 DSPI1_PCS1 — I/O EVDD msr — D12 SDHC_DAT0 PG7 PWM_B2 DSPI1_SOUT — I/O EVDD msr — B12 SDHC_CMD PG6 PWM_B0 DSPI1_SIN — I/O EVDD msr — C11 SDHC_CLK PG5 PWM_A0 DSPI1_SCK — O EVDD msr — A10 Signal name GPIO Alternate 1 Alternate 2 Pullup (U)
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Pin assignments and reset states Signal name GPIO Alternate 1 Alternate 2 Pullup (U)1 Pulldown (D) Direction2 Voltage domain Pad type3 196 MAPBGA 256 MAPBGA Table 5.
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Pin assignments and reset states Signal name GPIO Alternate 1 Alternate 2 Pullup (U)1 Pulldown (D) Direction2 Voltage domain Pad type3 196 MAPBGA 256 MAPBGA Table 5.
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Pin assignments and reset states 21 Configurable pull that is enabled and pulled down after reset. The ALLPST signal is available only on the 196 MAPBGA package and allows limited debug trace functionality compared to the 256 MAPBGA package. 23 If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these pins. 24 VSTBY is for optional standby lithium battery. If not used, connect to EVDD.
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Pin assignments and reset states 3.2 Pinout—196 MAPBGA The pinout for the MCF54410 package is shown below.
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Pin assignments and reset states 3.3 Pinout—256 MAPBGA The pinout for the MCF54415, MCF54416, MCF54417, and MCF54418 packages are shown below.
PAGE 21
Electrical characteristics 4 Electrical characteristics This document contains electrical specification tables and reference timing diagrams for the MCF5441x microprocessor. This section contains detailed information on AC/DC electrical characteristics and AC timing specifications. NOTE The specifications for this device in any other document are superseded by the specifications in this document. 4.1 Absolute maximum ratings Table 6.
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Electrical characteristics 4.2 Thermal characteristics Table 7.
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Electrical characteristics Solving equations 1 and 2 for K gives: 2 K = P D   T A  273C  + Q JMA  P D Eqn. 3 where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA. 4.3 ESD protection Table 8.
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Electrical characteristics Table 10. Power supply specifications (continued) Characteristic Symbol Pin Name Min Max Units EVDD EVDD 3.135 3.63 V USBVDD VDD_USBO VDD_USBH 3.135 3.63 V ADC supply voltage AVDD VDDA_ADC 3.135 3.63 V DAC supply voltage — VDDA_DAC_ ADC 3.135 3.63 V RTCVSTBY VSTBY_RTC 1.6 EVDD – 0.2V V External I/O pad supply voltage, nominal 3.3 V USB supply voltage, nominal 3.3 V RTC standby supply voltage Table 11.
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Electrical characteristics Table 11. I/O electrical specifications (continued) Characteristic Weak internal pull-up/pull-down device current1 Selectable weak internal pull-up/pull-down device current 1 2 Min Max Units IAPU 10 315 A IAPU 25 150 A — — 7 7 Input capacitance All input-only pins All input/output (three-state) pins Cin Output loading for CMOS pads (EVDD and FBVDD domains) Low drive High drive CL Output loading for SDRAMC pads (SDVDD domain) Low drive High drive CL 1 2 4.
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Electrical characteristics Table 12. Output pad slew rates (continued) Pad type1 Slew rate select field value Drive load (pF) Rise/fall time (ns) 50 1.2 200 6 50 9 200 14 50 17 200 23 50 110 200 120 50 1.1 200 2.6 50 2.4 200 5 50 5 200 8 50 16 200 21 msr 11 10 01 00 fsr 11 10 01 00 1 4.7 The ae pads are used for USB communication and are governed by usb.org specifications. They are not included in this table.
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Electrical characteristics 4.8 Oscillator and PLL electrical characteristics Reference Figure 9 for crystal circuits. Table 14.
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Electrical characteristics XOSC EXTAL XTAL RF RS Crystal or Resonator CC1L CL C2 Figure 9. Typical crystal circuit 4.9 Reset timing specifications Table 15 lists specifications for the reset timing parameters shown in Figure 10. Table 15. Reset and configuration override timing Num Characteristic Min Max Unit R11 RESET valid to FB_CLK (setup) 9 — ns R2 FB_CLK to RESET invalid (hold) 1.
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Electrical characteristics FB_CLK R1 R2 R3 RESET R4 R4 R9 RSTOUT R8 R5 R6 R7 BOOTMOD[1:0] Figure 10. RESET and configuration override timing 4.10 FlexBus timing specifications All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider of that frequency.
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Electrical characteristics S0 S1 S2 S3 FB_CLK FB1 FB3 FB_AD[Y:0] ADDR[Y:0] FB2 FB_AD[31:X] FB5 ADDR[31:X] DATA FB4 FB_R/W FB_ALE FB_TS FB_CSn, FB_OE, FB_BE/BWEn FB4 FB5 FB_TA FB_TSIZ[1:0] TSIZ[1:0] Note: 1 FB2 and FB3 output specifications are valid for all FB_AD[31:0], FB_R/W, FB_ALE, FB_TS, FB_CSn, FB_OE, FB_BE/BWEn, and FB_TSIZ[1:0]. 2 FB4 and FB5 input specifications are valid for all FB_AD[31:0] and FB_TA. Figure 11. FlexBus read timing MCF5441x ColdFire Microprocessor Data Sheet, Rev.
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Electrical characteristics S0 S1 S2 S3 FB_CLK FB1 FB3 ADDR[Y:0] FB_AD[Y:0] FB2 FB_AD[31:X] ADDR[31:X] DATA FB_R/W FB_ALE FB_TS FB_CSn, FB_BE/BWEn FB_OE FB4 FB5 FB_TA FB_TSIZ[1:0] TSIZ[1:0] Note: 1 FB2 and FB3 output specifications are valid for all FB_AD[31:0], FB_R/W, FB_ALE, FB_TS, FB_CSn, FB_OE, FB_BE/BWEn, and FB_TSIZ[1:0]. 2 FB4 and FB5 input specifications are valid for all FB_AD[31:0] and FB_TA. Figure 12. FlexBus write timing 4.
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Electrical characteristics Table 17. NFC timing specifications (continued) Num 1 Characteristic Symbol Min Max Unit NF7 NFC_ALE setup time tALS 1.5  tNFC — ns NF8 NFC_ALE hold time tALH tNFC — ns NF9 Data setup time tDS 0.5  tNFC – 4 — ns NF10 Data hold time tDH 0.5  tNFC – 10 — ns NF11 Write cycle time tWC tNFC — ns NF12 NFC_WE high hold time tWH 0.5  tNFC – 1 — ns NF13 Ready to NFC_RE low tRR 4.5  tNFC — ns NF14 NFC_RE pulse width tRP 0.
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Electrical characteristics NFC_CLE NF2 NF4 NF5 NFC_CE NF11 NF6 NF12 NFC_WE NF7 NF8 NFC_ALE NF10 NF9 NFC_IO[7:0] Address Figure 14. Address latch cycle timing NF3 NFC_CLE NF5 NFC_CE NF11 NF6 NF12 NFC_WE NF7 NFC_ALE NF9 NFC_IO[15:0] NF10 Data to NF Figure 15. Write data latch timing MCF5441x ColdFire Microprocessor Data Sheet, Rev.
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Electrical characteristics NF5 NFC_CE NF15 NF14 NF16 NFC_RE NF17 NFC_IO[15:0] NF10 Data from NF NF13 NFC_R/B Figure 16. Read data latch timing 4.12 DDR SDRAM controller timing specifications The following timing numbers must be followed to properly latch or drive data onto the SDRAM memory bus. All timing numbers are relative to the DQS byte lanes. Table 18. SDRAM timing specifications Num Characteristic Symbol Min Max Unit 100 250 MHz tSDCK 4.0 10.
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Electrical characteristics 3 4 5 6 7 This specification relates to the required input setup time of DDR memories. The microprocessor’s output setup should be larger than the input setup of the DDR memories. If it is not larger, then the input setup on the memory is in violation. SD_D[31:24] is relative to SD_DQS[3]; SD_D[23:16] is relative to SD_DQS[2] The first data beat is valid before the first rising edge of DQS and after the DQS write preamble.
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Electrical characteristics DD1 DD2 SD_CLK DD3 SD_CLK DD5 SD_CSn,SD_WE, SD_RAS, SD_CAS CL=2 CMD DD4 SD_A[13:0] CL=2.5 ROW COL DD9 DQS Read Preamble CL = 2 SD_DQS DQS Read Postamble DD10 CL = 2.5 SD_D[7:0] RD1 RD2 RD3 RD4 DQS Read DQS Read Preamble Postamble SD_DQS SD_D[7:0] RD1 RD2 RD3 RD4 Figure 18. DDR read timing 4.13 USB transceiver timing specifications The MCF5441x device is compliant with industry standard USB 2.0 specification. 4.
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Electrical characteristics All ULPI signals use pad type pad_fsr. The following timing specifications assume a pad slew rate setting of 11 and a load of 50 pF.1 Table 19. ULPI interface timing Num Characteristic Min Nominal Max Units USB_CLKIN operating frequency — 60 — MHz USB_CLKIN duty cycle — 50 — % U1 USB_CLKIN clock period — 16.67 — ns U2 Input setup (control and data) 5.0 — — ns U3 Input hold (control and data) 1.
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Electrical characteristics 4.15.1 eSDHC timing specifications Figure 20 depicts the timing of eSDHC, and Table 20 lists the eSDHC timing characteristics. Table 20.
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Electrical characteristics 4.15.2 eSDHC electrical DC characteristics Table 21 lists the eSDHC electrical DC characteristics. Table 21.
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Electrical characteristics 4.16.1 General timing requirements Figure 21 shows the timing of the SIM module, and Table 22 lists the timing parameters. 1/Sfreq SIM_CLK Sfall Srise Figure 21. SIM clock timing diagram Table 22. SIM timing specification—High Drive strength Num Description Symbol Min Max Unit 1 SIM clock frequency (SIM_CLK)1 Sfreq 0.
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Electrical characteristics 4.16.2.2 Cards with active-low reset The sequence of reset for this kind of card is as follows (see Figure 23): 1. 2. 3. 4. 5. After powerup, the clock signal is enabled on SIM_CLK (time T0) After 200 clock cycles, RX must be high.
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Electrical characteristics Table 23. Timing requirements for power-down sequence Num Description Symbol Min Max Unit 1 SIM reset to SIM clock stop Srst2clk 0.9  fCKIL 0.8 µs 2 SIM reset to SIM TX data low Srst2dat 1.8  fCKIL 1.2 µs 3 SIM reset to SIM voltage enable low Srst2ven 2.7  fCKIL 1.8 µs 4 SIM presence detect to SIM reset low Spd2rst 0.9  fCKIL 25 ns Spd2rst SIM_PD SIM_RST Srst2clk SIM_CLK Srst2dat SIM__TX Srst2ven SIM_VEN Figure 24.
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Electrical characteristics Table 24. SSI timing — master modes1 Num Description Symbol Min Max Units Notes tMCLK 15.
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Electrical characteristics S1 S2 S2 SSI_MCLK (Output) S3 SSI_BCLK (Output) S4 S4 S5 S6 SSI_FS (Output) S9 S10 SSI_FS (Input) S7 S7 S8 S8 SSI_TXD S9 S10 SSI_RXD Figure 25. SSI timing — master modes S11 SSI_BCLK (Input) S12 S12 S15 S16 SSI_FS (Output) S13 S14 SSI_FS (Input) S15 S16 S16 S15 SSI_TXD S17 S18 SSI_RXD Figure 26. SSI timing — slave modes 4.18 12-bit ADC specifications Table 26. ADC parameters1 Characteristic Name Min Typical Max 200kHz — 12MHz tADC 8.
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Electrical characteristics Table 26. ADC parameters1 (continued) Characteristic Differential non-linearity (10% to 90% input signal range)3 Name Min Typical Max Unit DNL — ±0.
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Electrical characteristics Table 27. DAC parameters1 (continued) Characteristic Name Min Typical Max Unit Integral non-linearity (497 to 3599) INL — — ±8.0 lsb Differential non-linearity (497 to 3599) DNL — — ±0.5 lsb Gain error (497 to 3599) EGAIN — ±0.
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Electrical characteristics Table 30. I2C output timing specifications between SCL and SDA Num I1 1 I21 I3 2 Characteristic Min Max Units Start condition hold time 6 — 1/fSYS Clock low period 10 — 1/fSYS I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) — — µs I41 Data hold time 7 — 1/fSYS I53 I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.
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Electrical characteristics 4.22.1 Receive signal timing specifications The following timing specs meet the requirements for MII and RMII interfaces for a range of transceiver devices. Table 31.
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Electrical characteristics E8 TXCLK (MII) / EXTAL (RMII) E7 E6 TXD[n:0] TXEN, TXER E5 Valid Data Figure 29. MII/RMII transmit signal timing diagram 4.22.3 Asynchronous input signal timing specifications Table 33. MII/RMII transmit signal timing Num Characteristic E9 CRS, COL minimum pulse width Min Max Unit 1.5 — TXCLK period CRS, COL E9 Figure 30. MII/RMII async inputs timing diagram 4.22.4 MDIO serial management timing specifications Table 34.
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Electrical characteristics E10 E11 MDC (Output) E11 E13 E12 Valid Data MDIO (Output) E14 MDIO (Input) E15 Valid Data Figure 31. MDIO serial management channel timing diagram 4.23 32-bit timer module timing specifications Table 35 lists timer module AC timings. Table 35. Timer module AC timing specifications Name 4.
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Electrical characteristics Table 36. DSPI module AC timing specifications1 (continued) Name Characteristic Symbol Min Max Unit DS6 DSPI_SCK to DSPI_SOUT invalid — –5 — ns DS7 DSPI_SIN to DSPI_SCK input setup — 6 — ns DS8 DSPI_SCK to DSPI_SIN input hold — 0 — ns Notes Slave Mode 1 2 3 4 5 — DSPI_SCK frequency fSCK — fSYS  8 MHz DS9 DSPI_SCK cycle time tSCK 8 fSYS — ns DS10 DSPI_SCK duty cycle — (tsck 2) – 2.0 (tsck 2) + 2.
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Electrical characteristics DS3 DS4 DSPI_PCSn DS1 DS2 DSPI_SCK (DCTARn[CPOL] = 0) DS2 DSPI_SCK (DCTARn[CPOL] = 1) DS7 DS8 DSPI_SIN First Data Data DS5 DSPI_SOUT Last Data DS6 First Data Data Last Data Figure 32. DSPI Classic SPI timing — master Mode DSPI_SS DS9 DSPI_SCK (DCTARn[CPOL] = 0) DS10 DS10 DSPI_SCK (DCTARn[CPOL] = 1) DS15 DSPI_SOUT DS12 First Data DS13 DSPI_SIN DS11 Data Last Data Data Last Data DS16 DS14 First Data Figure 33.
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Electrical characteristics 4.25 SBF timing specifications The Serial boot facility (SBF) provides a means to read configuration information and system boot code from a broad array of SPI-compatible EEPROMs, flashes, FRAMs, nVSRAMs, etc. Table 37 provides the AC timing specifications for the SBF. All SBF signals use pad type pad_msr. The following timing specifications assume a pad slew rate setting of 11 and a load of 50 pF.1 Table 37.
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Electrical characteristics 4.26 1-Wire timing specifications Specifications for the 1-Wire interface are provided by Maxim Integrated Products, Inc. Please refer to data sheet information for the appropriate device at www.maxim-ic.com. 4.27 General purpose I/O timing specifications Table 38.
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Electrical characteristics PST_CLK RG1 RG2 RGPIO Outputs RG3 RG4 RGPIO Inputs Figure 36. RGPIO timing 4.29 JTAG and boundary scan timing specifications All JTAG signals use pad type pad_msr except for TCLK which use pad type pad_fsr. The following timing specifications assume a pad slew rate setting of 11 and a load of 50 pF.1 Table 40.
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Electrical characteristics J2 J3 J3 VIH TCLK (input) VIL J4 J4 Figure 37. Test clock input timing TCLK VIL VIH J5 Data Inputs J6 Input Data Valid J7 Data Outputs Output Data Valid J8 Data Outputs J7 Data Outputs Output Data Valid Figure 38. Boundary scan (JTAG) timing TCLK VIL VIH J9 TDI TMS J10 Input Data Valid J11 TDO Output Data Valid J12 TDO J11 TDO Output Data Valid Figure 39. Test access port timing TCLK J14 TRST J13 Figure 40.
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Electrical characteristics 4.30 Debug AC timing specifications Table 41 lists specifications for the debug AC timing parameters shown in Figure 41 and Table 42. All debug signals use pad type pad_msr except for PSTCLK which use pad type pad_fsr. The following timing specifications assume a pad slew rate setting of 11 and a load of 50 pF.1 Table 41. Debug AC timing specification Num Min Max Units D0 PSTCLK cycle time 0.5 0.5 1/fSYS D1 PSTCLK rising to PSTDDATA valid — 3.
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Package information 5 Package information The latest package outline drawings are available on the product summary pages on http://www.freescale.com/coldfire. Table 42 lists the case outline numbers per device. Use these numbers in the web page’s keyword search engine to find the latest package outline drawings. Table 42.
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Revision history 7 Revision history Table 43 summarizes revisions to this document. Table 43. Revision history Rev. No. 2 Date Summary of changes 10 Jun 2009 In Section 2.2, “Supply voltage sequencing” added the following note: NOTE All I/O VDD pins must be powered on when the device is functioning, except when in standby mode. In standby mode, all I/O VDD pins, except VSTBY_RTC (battery), can be switched off. Added Section 3.2, “Pinout—169 MAPBGA” and Section 3.
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Revision history Table 43. Revision history (continued) Rev. No. Date Summary of changes 3 31 July 2009 Changed 169MAPBGA package to 196MAPBGA throughout. MCF54410 device now supports a single SSI module and one Ethernet controller with IEEE 1588 support 4 17 Aug 2009 Updated MCF5441x Signal Information and Muxing table with 196MAPBGA pin locations Changed SD_Dn pin locations on 256 MAPBGA package Added note to Section 4.
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