Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Pin assignments and reset states
Freescale Semiconductor10
NOTE
While most modules and functionalities between the 196 and 256 MAPBGA package are
the same, the following modules have been removed from 196 MAPBGA for pin space:
UART2, UART6, UART9, PWM, SSI1, SIM1, USB HOST, IRQ6, IRQ3, IRQ2,
FLEXCAN1, I2C1, ADC, DAC.
Other modifications to the 196 MAPBGA package are:
•SDRAMC
— One address line, SD_A14, is removed.
•SDHC
— Number of data lines for eSDHC have been reduced to 4 instead of 8.
•MAC
— Only MAC0_RMII mode is implemented.
Table 4. Special-case default signal functionality
Pin Default signal
FB_CLK, FB_OE
, FB_R/W,
FB_BE/BWE
[1:0],
FB_CS[5:4]
FB_CLK, FB_OE
, FB_R/W,
FB_BE/BWE
[1:0], FB_CS[5:4]
FB_ALE FB_ALE or FB_TS
(depending on RCON[3])
FB_BE/BWE3
Boot from NFC, NF_ALE.
Otherwise, FB_BE/BWE3
.
FB_BE/BWE2
Boot from NFC, NF_CLE.
Otherwise, FB_BE/BWE2.
FB_CS1 Boot from NFC, NFC_CE.
Otherwise, GPIO.
FB_CS0 Boot from FlexBus, FB_CS0.
Otherwise, GPIO.
FB_TA
Boot from NFC, NFC_R/B.
Otherwise, FB_TA.
ALLPST, PST[3:0],
DDATA[3:0]
ALLPST, PST[3:0], DDATA[3:0]
Table 5. MCF5441x Signal information and muxing
Signal name GPIO Alternate 1 Alternate 2
Pullup (U)
1
Pulldown (D)
Direction
2
Voltage doma in
Pad type
3
196 MAPBGA
256 MAPBGA
Reset
RESET — — — U
IEVDDssr K14 K15
RSTOUT —— ——OEVDDmsr P12 L16
Clock
EXTAL/
RMII_REF_CLK
—— ——
I
4
EVDD ae G14 G16