Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
Pin assignments and reset states
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 11
XTAL — — — —
OEVDD ae H14 H16
Mode selection
BOOTMOD[1:0] — — — —
I EVDD msr G5,H5 K5, L5
FlexBus
FB_AD[31:24]/
NFC_IO[15:8]
5
—— ——I/O FBVDD fsr A10, A9,
B9, C9, A8,
B8, C8, A7
B9, C8, A9,
B8, D8, A8,
D7, B7
FB_AD[23:16]/
NFC_IO[7:0]
5
—— ——I/O FBVDD fsr B7, C7, C6,
B6, A6, A5,
B5, A4
C7, A7, D6,
A6, B6, D5,
C6, A5
FB_AD[15:10] — — — —
6
I/O FBVDD fsr C5, A3, B4,
C4, B3, A2
B5, A4, A3,
D4, B4, C5
FB_AD[9:8] — — — U
7
I/O FBVDD fsr B2, C3 C4, B3
FB_AD[7:0] — — — — I/O FBVDD fsr D4, B1, C2,
D3, C1, D2,
E3, D1
C3, E4, D3,
E3, A2, B2,
C2, F3
FB_ALE PA7 FB_TS ——OFBVDD fsr E2 D2
FB_OE/
NFC_RE
PA6 FB_TBST/
NFC_RE
——OFBVDD fsr H1 F1
FB_R/W/
NFC_WE
PA 5 — — — OFBVDD fsr H2 G2
FB_TA PA4 — NFC_R/B U
8
OFBVDD fsr H3 H3
FB_BE/BWE3 PA 3 FB_CS3 FB_A1/
NFC_ALE
9
— OFBVDD fsr F3 C1
FB_BE/BWE2 PA 2 FB_CS2 FB_A0/
NFC_CLE
10
—OFBVDD fsr E1 E2
FB_BE/BWE[1:0] PA[1:0] FB_TSIZ[1:0] — — O FBVDD fsr F2, F1 D1, F4
FB_CLK PB7 — — — OFBVDD fsr G1 G1
FB_CS5 PB6 DACK1 ——OFBVDD fsr — F2
FB_CS4 PB5 DREQ1 ——OFBVDD fsr — B1
FB_CS1 PB4 — NFC_CE — OFBVDD fsr G3 E1
FB_CS0 PB3 — — — OFBVDD fsr G2 G3
I
2
C 0
I2C0_SCL
PB2 UART8_TXD CAN0_TX — I/O EVDD ssr H12 G15
I2C0_SDA PB1 UART8_RXD CAN0_RX — I/O EVDD ssr G12 G14
Table 5. MCF5441x Signal information and muxing (continued)
Signal name GPIO Alternate 1 Alternate 2
Pullup (U)
1
Pulldown (D)
Direction
2
Voltage d omain
Pad type
3
196 MAPBGA
256 MAPBGA